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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd161401 256-color, 1/80-duty lcd controller/driver with on-chip ram data sheet document no. s15726ej2v0ds00 (2nd edition) data published june 2002 ns cp(k) printed in japan description the pd161401 is an lcd controller/driver with ram and is capable of driving a full-dot lcd. it can display 256 colors on an rgb-stn color lcd. this lcd controller/driver can drive a full-dot lcd of up to 101 80 pixel with a single chip. features ? lcd driver with on-chip display ram ? logic power supply operation from +1.8 v to +3.6 v ? internal booster circuit: x 2 to x 7 selectable ? dot display ram: (101 x 80) x 8 bits ? 8 (r, g)/4 (b) grayscales selectable from 17 levels ? full-dot output: 303 segment lines and 80 common lines ? serial interface (si, scl) or 8-/16-bit parallel data input (i80 or m68 system interface) ? on-chip voltage divider resistor ? selectable bias value: 1/9 to 1/5 ? selectable duty ratio: 1/80, 1/72 and 1/64 (main duty) ? on-chip oscillator ordering information part number package pd161401w/p wafer/chip (supports cof) remark purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. the mark shows major revised points.
data sheet s15726ej2v0ds 2 pd161401 content 1. block diagram ................................................................................................................ ................... 5 2. pin configuration (pad layout) .............................................................................................. ....... 6 3. pin functions.............................................................................................................. ........................ 12 3.1 power supply pins........................................................................................................ ...................................12 3.2 logic circuit pins ....................................................................................................... .....................................13 3.3 driver pins .............................................................................................................. ..........................................15 4. pin i/o circuits and recommended connection of unused pins.................................... 16 5. functional description..................................................................................................... ............ 17 5.1 cpu interface ............................................................................................................. .......................................17 5.1.1 selecting interface type.................................................................................................. .........................17 5.1.2 parallel interface ........................................................................................................ .............................17 5.1.3 serial interface.......................................................................................................... ..............................19 5.1.4 chip select ............................................................................................................... ...............................19 5.1.5 accessing display data ram and internal registers ......................................................................... .......19 5.2 display data ram ......................................................................................................... ...................................21 5.2.1 display data ram .......................................................................................................... .........................21 5.2.2 x address circuit ......................................................................................................... ............................21 5.2.3 y address circuit ......................................................................................................... ............................23 5.2.4 column address circuit .................................................................................................... .......................24 5.2.5 common scan circuit ....................................................................................................... .......................25 5.2.6 display data latch circuit ................................................................................................ .........................28 5.2.7 arbitrary address area access (window access mode (was)) ...............................................................28 5.3 screen processing.............................................................................................................. .............................30 5.3.1 blink/reverse display circuit............................................................................................. ........................30 5.3.2 example of setting blink area............................................................................................. .....................33 5.4 oscillator ............................................................................................................... ...........................................33 5.5 display timing generator ................................................................................................. ..............................35 5.6 power supply circuit ........................................................................................................... ............................37 5.6.1 power supply circuit ...................................................................................................... ..........................37 5.6.2 booster circuit ........................................................................................................... ..............................37 5.6.3 voltage regulator circuit ................................................................................................. .........................39 5.6.4 level voltage control by operational amplifier ............................................................................ .............42 5.6.5 application example of power supply circuit ............................................................................... ............44 5.7 driving lcd .............................................................................................................. ........................................48 5.7.1 full-dot pulse modulation................................................................................................. .......................48
data sheet s15726ej2v0ds 3 pd161401 5.7.2 grayscale palette......................................................................................................... ...........................51 5.7.3 setting of display size ................................................................................................... ..........................52 5.7.4 setting of lcd n-line inversion and m-line shift.......................................................................... ............52 5.7.5 reverse driving between frames ............................................................................................ ................54 5.8 display mode............................................................................................................. .......................................55 5.8.1 selecting display mode .................................................................................................... .......................55 5.8.2 screen scrolling ....................................................................................................... ................................58 5.8.3 scroll setting examples ................................................................................................ ............................59 5.9 reset .................................................................................................................... .............................................61 6. commands ................................................................................................................... ......................... 63 6.1 control register 1 (r0).................................................................................................. ..................................64 6.2 control register 2 (r1).................................................................................................. ..................................65 6.3 reset command register (r3) .............................................................................................. .........................66 6.4 x address register (r4) .................................................................................................. ................................66 6.5 y address register (r5) .................................................................................................. ................................66 6.6 min.x address register (r7) ............................................................................................. ............................67 6.7 max.x address register (r8) ............................................................................................. ...........................67 6.8 min.y address register (r9) ............................................................................................. ............................67 6.9 max.y address register (r10) .................................................................................................. ....................68 6.10 display memory access register (r12).................................................................................... ...................68 6.11 main duty setting register (r14) ........................................................................................ .........................69 6.12 main duty n-line inversion register (r15)............................................................................... ....................69 6.13 main duty m-line shift register (r16) ................................................................................... .......................70 6.14 sub-duty setting register (r17) ......................................................................................... ..........................71 6.15 sub-duty n-line inversion register (r18) ................................................................................ ....................72 6.16 sub-duty m-line shift register (r19).................................................................................... ........................73 6.17 com scanning address setting register (r21)............................................................................. .............74 6.18 sub-duty start address register (r22)................................................................................... .....................77 6.19 scroll fixed area position register (r23) ............................................................................... ....................78 6.20 scroll fixed area width register (r27) .................................................................................. .....................78 6.21 scroll step number register (r31) ....................................................................................... .......................79 6.22 blink/reverse setting register (r37)........................................................................................... ................80 6.23 complementary color blink x address register (r38) ...................................................................... ........80 6.24 complementary color blink start line address register (r39)............................................................. ...81 6.25 complementary color blink end line address register (r40) .................................................................81 6.26 complementary color blink data memory register (r41) .................................................................... .....82 6.27 specified color blink x address register (r42) .......................................................................... ...............82 6.28 specified color blink start line address register (r43) ................................................................. ..........83 6.29 specified color blink end line address register (r44) .......................................................................... ..83 6.30 specified color blink data memory register (r45) ........................................................................ ............84 6.31 specified color setting register (r46) .................................................................................. ......................84
data sheet s15726ej2v0ds 4 pd161401 6.32 reverse x address register (r47) ........................................................................................ .......................84 6.33 reverse start line address register (r48) ............................................................................... ..................85 6.34 reverse end line address register (r49) ................................................................................. .................85 6.35 reverse data memory access register (r50)...................................................................................... .......86 6.36 power system control register 1 (r52) ................................................................................... ...................87 6.37 power system control register 2 (r53) ................................................................................... ...................88 6.38 power system control register 3 (r54) .......................................................................................... ............89 6.39 power system control register 4 (r55) ................................................................................... ...................90 6.40 power system control register 5 (r56) ................................................................................... ...................91 6.41 main electronic volume register (r57) .......................................................................................... .............92 6.42 sub-electronic volume register (r58).................................................................................... .....................92 6.43 ram test mode setting register (r61).................................................................................... ....................93 6.44 driving mode select register (r64) ...................................................................................... .......................93 6.45 main r grayscale data registers (r65 to r72) ............................................................................ ...............94 6.46 main g grayscale data registers (r73 to r80) ............................................................................ ...............95 6.47 main b grayscale data registers (r81 to r84) ............................................................................ ...............96 6.48 sub r grayscale data registers (r85 to r92)............................................................................. ................97 6.49 sub g grayscale data registers (r93 to r100) ............................................................................ ..............98 6.50 sub b grayscale data registers (r101 to r104)........................................................................... ..............99 7. pd161401 register list ......................................................................................................... ....... 100 8. power sequence............................................................................................................. ................ 102 8.1 power on sequence (with internal power supply, power on display on) ........................................103 8.2 power off sequence (with internal power supply) .......................................................................... .........105 8.3 power on sequence (with external driving power supply, power on display on)...........................106 8.4 power off sequence (with external driving power supply).................................................................. ...107 8.5 flow of v out and v lcd voltages from power on to power off .................................................................108 8.6 flow of v out and v lcd voltages in display output and halt/standby modes.........................................109 9. using ram test mode ........................................................................................................ ............. 110 10. electrical specifications................................................................................................. ....... 111 11. cpu interface (reference example)......................................................................................... ... 120
data sheet s15726ej2v0ds 5 pd161401 1. block diagram d15 to d8 d7(si) d6(scl) d5 to d0 rs /disp tout15 to tout0 /cs1 cs2 /rd(e) /wr(r,/w) m,/s fr frsync oscin1 oscin2 oscout oscsync c1 , c1 c5 , c5 + - + - vrs irs vr ampoutm ampouts seg 1 seg 303 o 1 o 80 vlcd vlc1 vlc2 vlc3 vlc4 v dd1 v dd2 v ss segment gray-scale control segment driver display data latch display data ram 101 x 8 x 80 bits blink & inverse data ram 303 bits data register d/a converter op amp. i/o buffer oscillator circuit dc/dc converter lcd voltage generator common driver common timing generator dof vout graphic control data control address control register command decorder gray-scale control logic control circuit vout2 timing generator ifm0 ifm1 tstrtst tstvihl tpwr0, tpwr1 remark /xxx is an active-low signal.
data sheet s15726ej2v0ds 6 pd161401 2. pin configuration (pad layout) ? ? ? ? pd161401w/p chip size: 2.57 x 16.05 mm 2 chip thickness: 485 m (typ.) m1 1 713 672 d u m m y o 80 d u m m y 671 dummy seg 303 seg 302 seg 301 seg 194 seg 193 dummy seg 192 seg 191 x y m2 317 318 359 d u m m y d u m m y 360 dummy seg 3 seg 2 seg 1 o 41 o 40 o 1 i/o side
data sheet s15726ej2v0ds 7 pd161401 details of pad and alignment mark pad type a type pad size (al): 39 x 71 m 2 typ. bump size : 33 x 65 m 2 typ. bump height: 17 m typ. b type pad size (al): 93 x 71 m 2 typ. bump size: 87 x 65 m 2 typ. bump height: 17 m typ. alignment mark (unit: m) xy m1 ? 1140.00 7560.00 m2 ? 1140.00 ? 7560.00 shape of mark (unit: m) mark center 80 (m1) 75 (m2)
data sheet s15726ej2v0ds 8 pd161401 table 2 ? ? ? ? 1 pad layout (1/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 1 dummy b -1144.50 7230.00 71 vss a -1144.50 4000.00 141 d11 a -1144.50 850.00 2 vss a -1144.50 7105.00 72 vss a -1144.50 3955.00 142 d11 a -1144.50 805.00 3 vss a -1144.50 7060.00 73 vss a -1144.50 3910.00 143 d10 a -1144.50 760.00 4 vss a -1144.50 7015.00 74 m, /s a -1144.50 3865.00 144 d10 a -1144.50 715.00 5 vout a -1144.50 6970.00 75 m, /s a -1144.50 3820.00 145 d10 a -1144.50 670.00 6 vout a -1144.50 6925.00 76 m, /s a -1144.50 3775.00 146 vss a -1144.50 625.00 7 vout a -1144.50 6880.00 77 vdd1 a -1144.50 3730.00 147 vss a -1144.50 580.00 8 vout2 a -1144.50 6835.00 78 vdd1 a -1144.50 3685.00 148 vss a -1144.50 535.00 9 vout2 a -1144.50 6790.00 79 vdd1 a -1144.50 3640.00 149 d9 a -1144.50 490.00 10 vout2 a -1144.50 6745.00 80 ifm0 a -1144.50 3595.00 150 d9 a -1144.50 445.00 11 vss a -1144.50 6700.00 81 ifm0 a -1144.50 3550.00 151 d9 a -1144.50 400.00 12 vss a -1144.50 6655.00 82 ifm0 a -1144.50 3505.00 152 d8 a -1144.50 355.00 13 vss a -1144.50 6610.00 83 vss a -1144.50 3460.00 153 d8 a -1144.50 310.00 14 c5 ? a -1144.50 6565.00 84 vss a -1144.50 3415.00 154 d8 a -1144.50 265.00 15 c5 ? a -1144.50 6520.00 85 vss a -1144.50 3370.00 155 vss a -1144.50 220.00 16 c5 ? a -1144.50 6475.00 86 ifm1 a -1144.50 3325.00 156 vss a -1144.50 175.00 17 c5+ a -1144.50 6430.00 87 ifm1 a -1144.50 3280.00 157 vss a -1144.50 130.00 18 c5+ a -1144.50 6385.00 88 ifm1 a -1144.50 3235.00 158 d7 a -1144.50 85.00 19 c5+ a -1144.50 6340.00 89 vdd1 a -1144.50 3190.00 159 d7 a -1144.50 40.00 20 c4 ? a -1144.50 6295.00 90 vdd1 a -1144.50 3145.00 160 d7 a -1144.50 -5.00 21 c4 ? a -1144.50 6250.00 91 vdd1 a -1144.50 3100.00 161 d6 a -1144.50 -50.00 22 c4 ? a -1144.50 6205.00 92 irs a -1144.50 3055.00 162 d6 a -1144.50 -95.00 23 c4+ a -1144.50 6160.00 93 irs a -1144.50 3010.00 163 d6 a -1144.50 -140.00 24 c4+ a -1144.50 6115.00 94 irs a -1144.50 2965.00 164 d5 a -1144.50 -185.00 25 c4+ a -1144.50 6070.00 95 vss a -1144.50 2920.00 165 d5 a -1144.50 -230.00 26 c3 ? a -1144.50 6025.00 96 vss a -1144.50 2875.00 166 d5 a -1144.50 -275.00 27 c3 ? a -1144.50 5980.00 97 vss a -1144.50 2830.00 167 vss a -1144.50 -320.00 28 c3 ? a -1144.50 5935.00 98 /cs1 a -1144.50 2785.00 168 vss a -1144.50 -365.00 29 c3+ a -1144.50 5890.00 99 /cs1 a -1144.50 2740.00 169 vss a -1144.50 -410.00 30 c3+ a -1144.50 5845.00 100 /cs1 a -1144.50 2695.00 170 d4 a -1144.50 -455.00 31 c3+ a -1144.50 5800.00 101 cs2 a -1144.50 2650.00 171 d4 a -1144.50 -500.00 32 c2 ? a -1144.50 5755.00 102 cs2 a -1144.50 2605.00 172 d4 a -1144.50 -545.00 33 c2 ? a -1144.50 5710.00 103 cs2 a -1144.50 2560.00 173 d3 a -1144.50 -590.00 34 c2 ? a -1144.50 5665.00 104 vdd1 a -1144.50 2515.00 174 d3 a -1144.50 -635.00 35 c2+ a -1144.50 5620.00 105 vdd1 a -1144.50 2470.00 175 d3 a -1144.50 -680.00 36 c2+ a -1144.50 5575.00 106 vdd1 a -1144.50 2425.00 176 d2 a -1144.50 -725.00 37 c2+ a -1144.50 5530.00 107 /disp a -1144.50 2380.00 177 d2 a -1144.50 -770.00 38 c1 ? a -1144.50 5485.00 108 /disp a -1144.50 2335.00 178 d2 a -1144.50 -815.00 39 c1 ? a -1144.50 5440.00 109 /disp a -1144.50 2290.00 179 vss a -1144.50 -860.00 40 c1 ? a -1144.50 5395.00 110 rs a -1144.50 2245.00 180 vss a -1144.50 -905.00 41 c1+ a -1144.50 5350.00 111 rs a -1144.50 2200.00 181 vss a -1144.50 -950.00 42 c1+ a -1144.50 5305.00 112 rs a -1144.50 2155.00 182 d1 a -1144.50 -995.00 43 c1+ a -1144.50 5260.00 113 vss a -1144.50 2110.00 183 d1 a -1144.50 -1040.00 44 vss a -1144.50 5215.00 114 vss a -1144.50 2065.00 184 d1 a -1144.50 -1085.00 45 vss a -1144.50 5170.00 115 vss a -1144.50 2020.00 185 d0 a -1144.50 -1130.00 46 vss a -1144.50 5125.00 116 /wr (r, /w) a -1144.50 1975.00 186 d0 a -1144.50 -1175.00 47 tpwr1 a -1144.50 5080.00 117 /wr (r, /w) a -1144.50 1930.00 187 d0 a -1144.50 -1220.00 48 tpwr1 a -1144.50 5035.00 118 /wr (r, /w) a -1144.50 1885.00 188 vss a -1144.50 -1265.00 49 tpwr1 a -1144.50 4990.00 119 /rd (e) a -1144.50 1840.00 189 vss a -1144.50 -1310.00 50 tpwr0 a -1144.50 4945.00 120 /rd (e) a -1144.50 1795.00 190 vss a -1144.50 -1355.00 51 tpwr0 a -1144.50 4900.00 121 /rd (e) a -1144.50 1750.00 191 frsync a -1144.50 -1400.00 52 tpwr0 a -1144.50 4855.00 122 vdd1 a -1144.50 1705.00 192 frsync a -1144.50 -1445.00 53 vrs a -1144.50 4810.00 123 vdd1 a -1144.50 1660.00 193 frsync a -1144.50 -1490.00 54 vrs a -1144.50 4765.00 124 vdd1 a -1144.50 1615.00 194 fr a -1144.50 -1535.00 55 vrs a -1144.50 44720.00 125 d15 a -1144.50 1570.00 195 fr a -1144.50 -1580.00 56 vss a -1144.50 4675.00 126 d15 a -1144.50 1525.00 196 fr a -1144.50 -1625.00 57 vss a -1144.50 4630.00 127 d15 a -1144.50 1480.00 197 dof a -1144.50 -1670.00 58 vss a -1144.50 4585.00 128 d14 a -1144.50 1435.00 198 dof a -1144.50 -1715.00 59 vss a -1144.50 4540.00 129 d14 a -1144.50 1390.00 199 dof a -1144.50 -1760.00 60 vss a -1144.50 4495.00 130 d14 a -1144.50 1345.00 200 oscsync a -1144.50 -1805.00 61 vss a -1144.50 4450.00 131 d13 a -1144.50 1300.00 201 oscsync a -1144.50 -1850.00 62 vdd2 a -1144.50 4405.00 132 d13 a -1144.50 1255.00 202 oscsync a -1144.50 -1895.00 63 vdd2 a -1144.50 4360.00 133 d13 a -1144.50 1210.00 203 vss a -1144.50 -1940.00 64 vdd2 a -1144.50 4315.00 134 vss a -1144.50 1165.00 204 vss a -1144.50 -1985.00 65 vdd1 a -1144.50 4270.00 135 vss a -1144.50 1120.00 205 vss a -1144.50 -2030.00 66 vdd1 a -1144.50 4225.00 136 vss a -1144.50 1075.00 206 oscin1 a -1144.50 -2075.00 67 vdd1 a -1144.50 4180.00 137 d12 a -1144.50 1030.00 207 oscin1 a -1144.50 -2120.00 68 vss a -1144.50 4135.00 138 d12 a -1144.50 985.00 208 oscin1 a -1144.50 -2165.00 69 vss a -1144.50 4090.00 139 d12 a -1144.50 940.00 209 vss a -1144.50 -2210.00 70 vss a -1144.50 4045.00 140 d11 a -1144.50 895.00 210 vss a -1144.50 -2255.00 pad layout [ m] pad layout [ m] pad layout [ m]
data sheet s15726ej2v0ds 9 pd161401 table 2 ? ? ? ? 1 pad layout (2/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 211 vss a -1144.50 -2300.00 281 vss a -1144.50 -5450.00 351 o8 a 505.00 -7773.00 212 oscin2 a -1144.50 -2345.00 282 vss a -1144.50 -5495.00 352 o7 a 550.00 -7773.00 213 oscin2 a -1144.50 -2390.00 283 vss a -1144.50 -5540.00 353 o6 a 595.00 -7773.00 214 oscin2 a -1144.50 -2435.00 284 vss a -1144.50 -5585.00 354 o5 a 640.00 -7773.00 215 vss a -1144.50 -2480.00 285 vss a -1144.50 -5630.00 355 o4 a 685.00 -7773.00 216 vss a -1144.50 -2525.00 286 vss a -1144.50 -5675.00 356 o3 a 730.00 -7773.00 217 vss a -1144.50 -2570.00 287 vr a -1144.50 -5720.00 357 o2 a 775.00 -7773.00 218 oscout a -1144.50 -2615.00 288 vr a -1144.50 -5765.00 358 o1 a 820.00 -7773.00 219 oscout a -1144.50 -2660.00 289 vr a -1144.50 -5810.00 359 dummy b 945.00 -7773.00 220 oscout a -1144.50 -2705.00 290 ampoutm a -1144.50 -5855.00 360 dummy b 1033.00 -7080.00 221 vss a -1144.50 -2750.00 291 ampoutm a -1144.50 -5900.00 361 seg1 a 1033.00 -6955.00 222 vss a -1144.50 -2795.00 292 ampoutm a -1144.50 -5945.00 362 seg2 a 1033.00 -6910.00 223 vss a -1144.50 -2840.00 293 vss a -1144.50 -5990.00 363 seg3 a 1033.00 -6865.00 224 tstrtst a -1144.50 -2885.00 294 vss a -1144.50 -6035.00 364 seg4 a 1033.00 -6820.00 225 tstrtst a -1144.50 -2930.00 295 vss a -1144.50 -6080.00 365 seg5 a 1033.00 -6775.00 226 tstrtst a -1144.50 -2975.00 296 ampouts a -1144.50 -6125.00 366 seg6 a 1033.00 -6730.00 227 tstvihl a -1144.50 -3020.00 297 ampouts a -1144.50 -6170.00 367 seg7 a 1033.00 -6685.00 228 tstvihl a -1144.50 -3065.00 298 ampouts a -1144.50 -6215.00 368 seg8 a 1033.00 -6640.00 229 tstvihl a -1144.50 -3110.00 299 vss a -1144.50 -6260.00 369 seg9 a 1033.00 -6595.00 230 tout15 a -1144.50 -3155.00 300 vss a -1144.50 -6305.00 370 seg10 a 1033.00 -6550.00 231 tout15 a -1144.50 -3200.00 301 vss a -1144.50 -6350.00 371 seg11 a 1033.00 -6505.00 232 tout15 a -1144.50 -3245.00 302 vlcd a -1144.50 -6395.00 372 seg12 a 1033.00 -6460.00 233 tout14 a -1144.50 -3290.00 303 vlcd a -1144.50 -6440.00 373 seg13 a 1033.00 -6415.00 234 tout14 a -1144.50 -3335.00 304 vlcd a -1144.50 -6485.00 374 seg14 a 1033.00 -6370.00 235 tout14 a -1144.50 -3380.00 305 vlc1 a -1144.50 -6530.00 375 seg15 a 1033.00 -6325.00 236 tout13 a -1144.50 -3425.00 306 vlc1 a -1144.50 -6575.00 376 seg16 a 1033.00 -6280.00 237 tout13 a -1144.50 -3470.00 307 vlc1 a -1144.50 -6620.00 377 seg17 a 1033.00 -6235.00 238 tout13 a -1144.50 -3515.00 308 vlc2 a -1144.50 -6665.00 378 seg18 a 1033.00 -6190.00 239 tout12 a -1144.50 -3560.00 309 vlc2 a -1144.50 -6710.00 379 seg19 a 1033.00 -6145.00 240 tout12 a -1144.50 -3605.00 310 vlc2 a -1144.50 -6755.00 380 seg20 a 1033.00 -6100.00 241 tout12 a -1144.50 -3650.00 311 vlc3 a -1144.50 -6800.00 381 seg21 a 1033.00 -6055.00 242 tout11 a -1144.50 -3695.00 312 vlc3 a -1144.50 -6845.00 382 seg22 a 1033.00 -6010.00 243 tout11 a -1144.50 -3740.00 313 vlc3 a -1144.50 -6890.00 383 seg23 a 1033.00 -5965.00 244 tout11 a -1144.50 -3785.00 314 vlc4 a -1144.50 -6935.00 384 seg24 a 1033.00 -5920.00 245 tout10 a -1144.50 -3830.00 315 vlc4 a -1144.50 -6980.00 385 seg25 a 1033.00 -5875.00 246 tout10 a -1144.50 -3875.00 316 vlc4 a -1144.50 -7025.00 386 seg26 a 1033.00 -5830.00 247 tout10 a -1144.50 -3920.00 317 dummy b -1144.50 -7150.00 387 seg27 a 1033.00 -5785.00 248 tout9 a -1144.50 -3965.00 318 dummy b -1060.00 -7773.00 388 seg28 a 1033.00 -5740.00 249 tout9 a -1144.50 -4010.00 319 o40 a -935.00 -7773.00 389 seg29 a 1033.00 -5695.00 250 tout9 a -1144.50 -4055.00 320 o39 a -890.00 -7773.00 390 seg30 a 1033.00 -5650.00 251 tout8 a -1144.50 -4100.00 321 o38 a -845.00 -7773.00 391 seg31 a 1033.00 -5605.00 252 tout8 a -1144.50 -4145.00 322 o37 a -800.00 -7773.00 392 seg32 a 1033.00 -5560.00 253 tout8 a -1144.50 -4190.00 323 o36 a -755.00 -7773.00 393 seg33 a 1033.00 -5515.00 254 tout7 a -1144.50 -4235.00 324 o35 a -710.00 -7773.00 394 seg34 a 1033.00 -5470.00 255 tout7 a -1144.50 -4280.00 325 o34 a -665.00 -7773.00 395 seg35 a 1033.00 -5425.00 256 tout7 a -1144.50 -4325.00 326 o33 a -620.00 -7773.00 396 seg36 a 1033.00 -5380.00 257 tout6 a -1144.50 -4370.00 327 o32 a -575.00 -7773.00 397 seg37 a 1033.00 -5335.00 258 tout6 a -1144.50 -4415.00 328 o31 a -530.00 -7773.00 398 seg38 a 1033.00 -5290.00 259 tout6 a -1144.50 -4460.00 329 o30 a -485.00 -7773.00 399 seg39 a 1033.00 -5245.00 260 tout5 a -1144.50 -4505.00 330 o29 a -440.00 -7773.00 400 seg40 a 1033.00 -5200.00 261 tout5 a -1144.50 -4550.00 331 o28 a -395.00 -7773.00 401 seg41 a 1033.00 -5155.00 262 tout5 a -1144.50 -4595.00 332 o27 a -350.00 -7773.00 402 seg42 a 1033.00 -5110.00 263 tout4 a -1144.50 -4640.00 333 o26 a -305.00 -7773.00 403 seg43 a 1033.00 -5065.00 264 tout4 a -1144.50 -4685.00 334 o25 a -260.00 -7773.00 404 seg44 a 1033.00 -5020.00 265 tout4 a -1144.50 -4730.00 335 o24 a -215.00 -7773.00 405 seg45 a 1033.00 -4975.00 266 tout3 a -1144.50 -4775.00 336 o23 a -170.00 -7773.00 406 seg46 a 1033.00 -4930.00 267 tout3 a -1144.50 -4820.00 337 o22 a -125.00 -7773.00 407 seg47 a 1033.00 -4885.00 268 tout3 a -1144.50 -4865.00 338 o21 a -80.00 -7773.00 408 seg48 a 1033.00 -4840.00 269 tout2 a -1144.50 -4910.00 339 o20 a -35.00 -7773.00 409 seg49 a 1033.00 -4795.00 270 tout2 a -1144.50 -4955.00 340 o19 a 10.00 -7773.00 410 seg50 a 1033.00 -4750.00 271 tout2 a -1144.50 -5000.00 341 o18 a 55.00 -7773.00 411 seg51 a 1033.00 -4705.00 272 tout1 a -1144.50 -5045.00 342 o17 a 100.00 -7773.00 412 seg52 a 1033.00 -4660.00 273 tout1 a -1144.50 -5090.00 343 o16 a 145.00 -7773.00 413 seg53 a 1033.00 -4615.00 274 tout1 a -1144.50 -5135.00 344 o15 a 190.00 -7773.00 414 seg54 a 1033.00 -4570.00 275 tout0 a -1144.50 -5180.00 345 o14 a 235.00 -7773.00 415 seg55 a 1033.00 -4525.00 276 tout0 a -1144.50 -5225.00 346 o13 a 280.00 -7773.00 416 seg56 a 1033.00 -4480.00 277 tout0 a -1144.50 -5270.00 347 o12 a 325.00 -7773.00 417 seg57 a 1033.00 -4435.00 278 vss a -1144.50 -5315.00 348 o11 a 370.00 -7773.00 418 seg58 a 1033.00 -4390.00 279 vss a -1144.50 -5360.00 349 o10 a 415.00 -7773.00 419 seg59 a 1033.00 -4345.00 280 vss a -1144.50 -5405.00 350 o9 a 460.00 -7773.00 420 seg60 a 1033.00 -4300.00 pad layout [ m] pad layout [ m] pad layout [ m]
data sheet s15726ej2v0ds 10 pd161401 table 2 ? ? ? ? 1 pad layout (3/4) pad pad name pad pad pad name pad pad pad name pad no. type x y no. type x y no. type x y 421 seg61 a 1033.00 -4255.00 491 seg131 a 1033.00 -1105.00 561 seg194 a 1033.00 2045.00 422 seg62 a 1033.00 -4210.00 492 seg132 a 1033.00 -1060.00 562 seg195 a 1033.00 2090.00 423 seg63 a 1033.00 -4165.00 493 seg133 a 1033.00 -1015.00 563 seg196 a 1033.00 2135.00 424 seg64 a 1033.00 -4120.00 494 seg134 a 1033.00 -970.00 564 seg197 a 1033.00 2180.00 425 seg65 a 1033.00 -4075.00 495 seg135 a 1033.00 -925.00 565 seg198 a 1033.00 2225.00 426 seg66 a 1033.00 -4030.00 496 seg136 a 1033.00 -880.00 566 seg199 a 1033.00 2270.00 427 seg67 a 1033.00 -3985.00 497 seg137 a 1033.00 -835.00 567 seg200 a 1033.00 2315.00 428 seg68 a 1033.00 -3940.00 498 seg138 a 1033.00 -790.00 568 seg201 a 1033.00 2360.00 429 seg69 a 1033.00 -3895.00 499 seg139 a 1033.00 -745.00 569 seg202 a 1033.00 2405.00 430 seg70 a 1033.00 -3850.00 500 seg140 a 1033.00 -700.00 570 seg203 a 1033.00 2450.00 431 seg71 a 1033.00 -3805.00 501 seg141 a 1033.00 -655.00 571 seg204 a 1033.00 2495.00 432 seg72 a 1033.00 -3760.00 502 seg142 a 1033.00 -610.00 572 seg205 a 1033.00 2540.00 433 seg73 a 1033.00 -3715.00 503 seg143 a 1033.00 -565.00 573 seg206 a 1033.00 2585.00 434 seg74 a 1033.00 -3670.00 504 seg144 a 1033.00 -520.00 574 seg207 a 1033.00 2630.00 435 seg75 a 1033.00 -3625.00 505 seg145 a 1033.00 -475.00 575 seg208 a 1033.00 2675.00 436 seg76 a 1033.00 -3580.00 506 seg146 a 1033.00 -430.00 576 seg209 a 1033.00 2720.00 437 seg77 a 1033.00 -3535.00 507 seg147 a 1033.00 -385.00 577 seg210 a 1033.00 2765.00 438 seg78 a 1033.00 -3490.00 508 seg148 a 1033.00 -340.00 578 seg211 a 1033.00 2810.00 439 seg79 a 1033.00 -3445.00 509 seg149 a 1033.00 -295.00 579 seg212 a 1033.00 2855.00 440 seg80 a 1033.00 -3400.00 510 seg150 a 1033.00 -250.00 580 seg213 a 1033.00 2900.00 441 seg81 a 1033.00 -3355.00 511 seg151 a 1033.00 -205.00 581 seg214 a 1033.00 2945.00 442 seg82 a 1033.00 -3310.00 512 seg152 a 1033.00 -160.00 582 seg215 a 1033.00 2990.00 443 seg83 a 1033.00 -3265.00 513 seg153 a 1033.00 -115.00 583 seg216 a 1033.00 3035.00 444 seg84 a 1033.00 -3220.00 514 seg154 a 1033.00 -70.00 584 seg217 a 1033.00 3080.00 445 seg85 a 1033.00 -3175.00 515 seg155 a 1033.00 -25.00 585 seg218 a 1033.00 3125.00 446 seg86 a 1033.00 -3130.00 516 seg156 a 1033.00 20.00 586 seg219 a 1033.00 3170.00 447 seg87 a 1033.00 -3085.00 517 seg157 a 1033.00 65.00 587 seg220 a 1033.00 3215.00 448 seg88 a 1033.00 -3040.00 518 seg158 a 1033.00 110.00 588 seg221 a 1033.00 3260.00 449 seg89 a 1033.00 -2995.00 519 seg159 a 1033.00 155.00 589 seg222 a 1033.00 3305.00 450 seg90 a 1033.00 -2950.00 520 seg160 a 1033.00 200.00 590 seg223 a 1033.00 3350.00 451 seg91 a 1033.00 -2905.00 521 seg161 a 1033.00 245.00 591 seg224 a 1033.00 3395.00 452 seg92 a 1033.00 -2860.00 522 seg162 a 1033.00 290.00 592 seg225 a 1033.00 3440.00 453 seg93 a 1033.00 -2815.00 523 seg163 a 1033.00 335.00 593 seg226 a 1033.00 3485.00 454 seg94 a 1033.00 -2770.00 524 seg164 a 1033.00 380.00 594 seg227 a 1033.00 3530.00 455 seg95 a 1033.00 -2725.00 525 seg165 a 1033.00 425.00 595 seg228 a 1033.00 3575.00 456 seg96 a 1033.00 -2680.00 526 seg166 a 1033.00 470.00 596 seg229 a 1033.00 3620.00 457 seg97 a 1033.00 -2635.00 527 seg167 a 1033.00 515.00 597 seg230 a 1033.00 3665.00 458 seg98 a 1033.00 -2590.00 528 seg168 a 1033.00 560.00 598 seg231 a 1033.00 3710.00 459 seg99 a 1033.00 -2545.00 529 seg169 a 1033.00 605.00 599 seg232 a 1033.00 3755.00 460 seg100 a 1033.00 -2500.00 530 seg170 a 1033.00 650.00 600 seg233 a 1033.00 3800.00 461 seg101 a 1033.00 -2455.00 531 seg171 a 1033.00 695.00 601 seg234 a 1033.00 3845.00 462 seg102 a 1033.00 -2410.00 532 seg172 a 1033.00 740.00 602 seg235 a 1033.00 3890.00 463 seg103 a 1033.00 -2365.00 533 seg173 a 1033.00 785.00 603 seg236 a 1033.00 3935.00 464 seg104 a 1033.00 -2320.00 534 seg174 a 1033.00 830.00 604 seg237 a 1033.00 3980.00 465 seg105 a 1033.00 -2275.00 535 seg175 a 1033.00 875.00 605 seg238 a 1033.00 4025.00 466 seg106 a 1033.00 -2230.00 536 seg176 a 1033.00 920.00 606 seg239 a 1033.00 4070.00 467 seg107 a 1033.00 -2185.00 537 seg177 a 1033.00 965.00 607 seg240 a 1033.00 4115.00 468 seg108 a 1033.00 -2140.00 538 seg178 a 1033.00 1010.00 608 seg241 a 1033.00 4160.00 469 seg109 a 1033.00 -2095.00 539 seg179 a 1033.00 1055.00 609 seg242 a 1033.00 4205.00 470 seg110 a 1033.00 -2050.00 540 seg180 a 1033.00 1100.00 610 seg243 a 1033.00 4250.00 471 seg111 a 1033.00 -2005.00 541 seg181 a 1033.00 1145.00 611 seg244 a 1033.00 4295.00 472 seg112 a 1033.00 -1960.00 542 seg182 a 1033.00 1190.00 612 seg245 a 1033.00 4340.00 473 seg113 a 1033.00 -1915.00 543 seg183 a 1033.00 1235.00 613 seg246 a 1033.00 4385.00 474 seg114 a 1033.00 -1870.00 544 seg184 a 1033.00 1280.00 614 seg247 a 1033.00 4430.00 475 seg115 a 1033.00 -1825.00 545 seg185 a 1033.00 1325.00 615 seg248 a 1033.00 4475.00 476 seg116 a 1033.00 -1780.00 546 seg186 a 1033.00 1370.00 616 seg249 a 1033.00 4520.00 477 seg117 a 1033.00 -1735.00 547 seg187 a 1033.00 1415.00 617 seg250 a 1033.00 4565.00 478 seg118 a 1033.00 -1690.00 548 seg188 a 1033.00 1460.00 618 seg251 a 1033.00 4610.00 479 seg119 a 1033.00 -1645.00 549 seg189 a 1033.00 1505.00 619 seg252 a 1033.00 4655.00 480 seg120 a 1033.00 -1600.00 550 seg190 a 1033.00 1550.00 620 seg253 a 1033.00 4700.00 481 seg121 a 1033.00 -1555.00 551 seg191 a 1033.00 1595.00 621 seg254 a 1033.00 4745.00 482 seg122 a 1033.00 -1510.00 552 seg192 a 1033.00 1640.00 622 seg255 a 1033.00 4790.00 483 seg123 a 1033.00 -1465.00 553 dummy a 1033.00 1685.00 623 seg256 a 1033.00 4835.00 484 seg124 a 1033.00 -1420.00 554 dummy a 1033.00 1730.00 624 seg257 a 1033.00 4880.00 485 seg125 a 1033.00 -1375.00 555 dummy a 1033.00 1775.00 625 seg258 a 1033.00 4925.00 486 seg126 a 1033.00 -1330.00 556 dummy a 1033.00 1820.00 626 seg259 a 1033.00 4970.00 487 seg127 a 1033.00 1285.00 557 dummy a 1033.00 1865.00 627 seg260 a 1033.00 5015.00 488 seg128 a 1033.00 -1240.00 558 dummy a 1033.00 1910.00 628 seg261 a 1033.00 5060.00 489 seg129 a 1033.00 -1195.00 559 dummy a 1033.00 1955.00 629 seg262 a 1033.00 5105.00 490 seg130 a 1033.00 -1150.00 560 seg193 a 1033.00 2000.00 630 seg263 a 1033.00 5150.00 pad layout [ m] pad layout [ m] pad layout [ m]
data sheet s15726ej2v0ds 11 pd161401 table 2 ? ? ? ? 1 pad layout (4/4) pad pad name pad pad pad name pad no. type x y no. type x y 631 seg264 a 1033.00 5195.00 701 o69 a -435.00 7773.00 632 seg265 a 1033.00 5240.00 702 o70 a -480.00 7773.00 633 seg266 a 1033.00 5285.00 703 o71 a -525.00 7773.00 634 seg267 a 1033.00 5330.00 704 o72 a -570.00 7773.00 635 seg268 a 1033.00 5375.00 705 o73 a -615.00 7773.00 636 seg269 a 1033.00 5420.00 706 o74 a -660.00 7773.00 637 seg270 a 1033.00 5465.00 707 o75 a -705.00 7773.00 638 seg271 a 1033.00 5510.00 708 o76 a -750.00 7773.00 639 seg272 a 1033.00 5555.00 709 o77 a -795.00 7773.00 640 seg273 a 1033.00 5600.00 710 o78 a -840.00 7773.00 641 seg274 a 1033.00 5645.00 711 o79 a -885.00 7773.00 642 seg275 a 1033.00 5690.00 712 o80 a -930.00 7773.00 643 seg276 a 1033.00 5735.00 713 dummy b -1055.00 7773.00 644 seg277 a 1033.00 5780.00 645 seg278 a 1033.00 5825.00 646 seg279 a 1033.00 5870.00 647 seg280 a 1033.00 5915.00 648 seg281 a 1033.00 5960.00 649 seg282 a 1033.00 6005.00 650 seg283 a 1033.00 6050.00 651 seg284 a 1033.00 6095.00 652 seg285 a 1033.00 6140.00 653 seg286 a 1033.00 6185.00 654 seg287 a 1033.00 6230.00 655 seg288 a 1033.00 6275.00 656 seg289 a 1033.00 6320.00 657 seg290 a 1033.00 6365.00 658 seg291 a 1033.00 6410.00 659 seg292 a 1033.00 6455.00 660 seg293 a 1033.00 6500.00 661 seg294 a 1033.00 6545.00 662 seg295 a 1033.00 6590.00 663 seg296 a 1033.00 6635.00 664 seg297 a 1033.00 6680.00 665 seg298 a 1033.00 6725.00 666 seg299 a 1033.00 6770.00 667 seg300 a 1033.00 6815.00 668 seg301 a 1033.00 6860.00 669 seg302 a 1033.00 6905.00 670 seg303 a 1033.00 6950.00 671 dummy a 1033.00 7075.00 672 dummy a 950.00 7773.00 673 o41 a 825.00 7773.00 674 o42 a 780.00 7773.00 675 o43 a 735.00 7773.00 676 o44 a 690.00 7773.00 677 o45 a 645.00 7773.00 678 o46 a 600.00 7773.00 679 o47 a 555.00 7773.00 680 o48 a 510.00 7773.00 681 o49 a 465.00 7773.00 682 o50 a 420.00 7773.00 683 o51 a 375.00 7773.00 684 o52 a 330.00 7773.00 685 o53 a 285.00 7773.00 686 o54 a 240.00 7773.00 687 o55 a 195.00 7773.00 688 o56 a 150.00 7773.00 689 o57 a 105.00 7773.00 690 o58 a 60.00 7773.00 691 o59 a 15.00 7773.00 692 o60 a -30.00 7773.00 693 o61 a -75.00 7773.00 694 o62 a -120.00 7773.00 695 o63 a -165.00 7773.00 696 o64 a -210.00 7773.00 697 o65 a -255.00 7773.00 698 o66 a -300.00 7773.00 699 o67 a -345.00 7773.00 700 o68 a -390.00 7773.00 pad layout [ m] pad layout [ m]
data sheet s15726ej2v0ds 12 pd161401 3. pin functions 3.1 power supply pins symbol pin name pin no. i/o description v dd1 logic power supply 65 to 67, 77 to 79, 89 to 91,104 to 106, 122 to 124 ? supplies power to the logic circuit. v dd2 booster circuit power supply 62 to 64 ? supplies power to the booster circuit. v ss logic and driver ground pin 2 to 4, 11 to 13, 44 to 46, 56 to 61, 68 to 73, 83 to 85, 95 to 97, 113 to 115, 134 to 136, 146 to 148, 155 to 157, 167 to 169, 179 to 181, 188 to 190, 203 to 205, 209 to 211, 215 to 217, 221 to 223, 278 to 286, 293 to 295, 299 to 301 ? ground pin for the logic and driver circuits. v out , v out2 driver power supply 5 to 7, 8 to 10 ? supply power to the driver (output pins of the internal booster circuit). connect a 1 f capacitor between gnd and these pins. when the internal booster circuit is not used, the driver power can be directly input to the v out pin. at this time, leave v out2 open. v lcd , v lc1 to v lc4 driver reference power supply 302 to 304, 305 to 316 ? supply the reference power for driving the lcd. connect a capacitor between gnd and these pins when an internal bias is selected. c 1 + , c 1 ? c 2 + , c 2 ? c 3 + , c 3 ? c 4 + , c 4 ? c 5 + , c 5 ? booster capacitor connection pin 43 to 14 ? these pins are used to connect capacitors for the internal booster circuit. connect a 1 f capacitor between the corresponding (+) and ( ? ) pins.
data sheet s15726ej2v0ds 13 pd161401 3.2 logic circuit pins (1/3) symbol pin name pin no. i/o description /cs1, cs2 chip select 98 to 100, 101 to 103 input these pins are chip select signal pins. when /cs1 = l (cs2 = h), the chip is active, and data/command can be input or output and i/o manipulated. /rd (e) read (enable) 119 to 121 input when i80 system parallel data transfer is selected (/rd), read is enabled by this signal. when this pin is l, data is output to the data bus. when m68 system parallel data transfer is selected (e), this pin inputs an enable signal that triggers data write or read. but in the pd161401, the data of the display access memory register, the complementary color blink data memory register, the specified color blink data memory register and the reverse data memory access register (r12, r41, r45, r50) cannot be read. /wr (r,/w) write (read/write) 116 to 118 input when i80 system parallel data transfer is selected (/wr), write is enabled by this signal. data is written at the rising edge of this signal. when m68 system parallel data transfer is selected (r, /w), this pin determines the data transfer direction, as follows: 0: write 1: read selects an interface mode ifm1 ifm0 interface mode llserial l h setting prohibited h l i80 series parallel h h m68 series parallel ifm0, ifm1 interface selection 86 to 88, 80 to 82 input d 0 to d 15 (si) (scl) data bus (serial input) (serial clock) 187 to 182, 178 to 170, 166 to 158, 154 to 149, 145 to 137, 133 to 125 i/o this is a bi-directional data bus connected to an 8- or 16-bit standard cpu bus. when the serial interface mode is selected (ifm1, ifm0 = l, l), d 7 functions as a serial data input pin (si), and d 6 serves as a serial clock input pin (scl). at this time, d 0 to d 5 and d 8 to d 15 go into a high-impedance state. when the 8-bit data bus is selected, only d 0 to d 7 are used, and d 8 to d 15 go into a high-impedance state. data is input starting from its higher byte, followed by the lower byte. if the chip is not selected, all d 0 to d 15 go into a high-impedance state. rs index register/data command selection 110 to 112 input this pin is usually connected to the least significant bit of a standard cpu address bus to identify whether data is an index register or data/command. rs = h: indicates that d 0 to d 15 are data/command. rs = l: indicates that d 0 to d 15 are an index register.
data sheet s15726ej2v0ds 14 pd161401 (2/3) symbol pin name pin no. i/o description /disp reset 107 to 109 input making /disp low initializes the disp flag in the control register 1 (r0) and turns off the display. when the serial interface is used, the write counter is also initialized. making /disp high enables writing. to light the display after it has been turned off by this pin, make /disp high and set the disp flag to 1. fr frame signal 194 to 196 i/o this pin inputs or outputs a liquid crystal ac signal. m,/s = h : output m,/s = l : input when two or more pd161401s are used in master/slave mode, the respective fr pins must be connected to each other. fr sync frame sync signal 191 to 193 i/o this pin inputs or outputs a liquid crystal ac sync signal. m,/s = h : output m,/s = l : input when two or more pd161401s are used in master/slave mode, the respective fr sync pins must be connected to each other. dof display blink 197 to 199 i/o this pin controls blinking of the lcd. m,/s = h : output m,/s = l : input when two or more pd161401s are used in master/slave mode, the respective dof pins must be connected to each other. this pin selects master or slave mode. in the master mode, it outputs a timing signal necessary for driving the lcd. in the slave mode, this timing signal is input from an external source to synchronize the lcd. m,/s = h : master mode m,/s = l : slave mode the status of each pin, including this pin, and the power circuit is as follows depending on the status of the m,/s pin. m,/s power circuit fr fr sync dof h enabled output output output l disabled input input input m,/s master/slave 74 to 76 input irs v lcd adjustment 92 to 94 input this pin selects the resistor used to adjust the v lcd voltage level. irs = h: the internal resistor is used. irs = l: the internal resistor is not used. the v lcd voltage level is adjusted by an external voltage divider resistor connected to the v r pin. this pin is enabled only when the master operation mode is selected. if the slave mode is selected, this pin is fixed to h or l.
data sheet s15726ej2v0ds 15 pd161401 (3/3) symbol pin name pin no. i/o description osc in1 206 to 208 input osc in2 212 to 214 input osc out oscillation signal pin 218 to 220 output these pins are connected with a resistor inserted between osc in1 and osc out , and between osc in2 and osc out . when an external oscillator is used, input a clock signal to the osc in pin and leave the osc out pin open. osc sync display clock output 200 to 202 output this pin outputs a clock for display. when using the pd161401 in the master or slave mode, refer to 5.4 oscillator . t out0 to t out15 test output 230 to 277 output these pins are used when the pd161401 is in the test mode. usually, leave these pins open. tstrtst, tstvihl test input pin 224 to 226, 227 to 229 input these pins are used to set the pd161401 in the test mode. usually, connect these pins to v ss . tpwr 0 , tpwr 1 test input/output pin 50 to 52, 47 to 49 i/o these pins are used to input/output test signals when the pd161401 is in the test mode. usually, leave these pins open. 3.3 driver pins symbol pin name pin no. i/o description seg 1 to seg 303 segment 361 to 670 output these pins output segment signals. o 1 to o 80 common 319 to 358, 673 to 712 output these pins output common signals. v rs 53 to 55 v r operational amplifier input 287 to 289 input these are the input pins of the operational amplifier that adjusts the lcd driving voltage. v rs is used to input the reference voltage of the amplifier for lcd voltage adjustment. v r is used to connect a feedback resistor for the operational amplifier. the feedback resistor is connected between this pin and gnd, amp outm , or amp outs . this pin is enabled only when the internal divider resistor for v lcd voltage adjustment is not used (irs = l). when the internal divider resistor is used (irs = h), this pin is not used. amp outm 290 to 292 amp outs operational amplifier output 296 to 298 output these pins are the output pins of the operational amplifier that adjusts the lcd driving voltage. the signals output by these pins are connected to the lcd driving voltage adjuster resistor (refer to 5.6.3 voltage regulator circuit ) only when the internal resistor for lcd voltage adjustment is not used (irs = l). it is recommended to connect a capacitor of 0.01 to 0.1 f to these pins to stabilize the output of the internal operational amplifier. dummy dummy pin 1, 317, 318, 359, 360, 553 to 559, 671, 672, 713 ? these pins are not connected to the internal circuit.
data sheet s15726ej2v0ds 16 pd161401 4. pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in the table below. symbol input type i/o recommended of unused pins note /cs1 schmitt-trigger a input connect this pin to v ss . ? cs2 schmitt-trigger a input connect this pin to v dd1 . ? /rd(e) schmitt-trigger a input connect to v dd1 (i80 system interface), or to v dd1 or v ss (serial interface). ? /wr(r,/w) schmitt-trigger a input connect to v dd1 or v ss (serial interface). ? ifm1, ifm0 schmitt-trigger a input mode setting pin 1 d 0 to d 5 schmitt-trigger b i/o leave open. ? d 6 (scl) schmitt-trigger b i/o ?? d 7 (si) schmitt-trigger b i/o ?? d 8 to d 15 schmitt-trigger b i/o leave open. ? rs schmitt-trigger a input register setting pin 2 /disp schmitt-trigger c input connect to v dd1 . ? fr schmitt-trigger a i/o leave open (in master mode, m,/s = h). ? fr sync schmitt-trigger a i/o leave open (in master mode, m,/s = h). ? dof schmitt-trigger a i/o leave open (in master mode, m,/s = h). ? m,/s schmitt-trigger a input mode setting pin 1 irs schmitt-trigger a input mode setting pin 1 osc in1 schmitt-trigger a input connect to v dd1 or v ss . ? osc in2 schmitt-trigger a input connect to v dd1 or v ss . ? osc out ? output leave open (when an external clock is used). ? osc sync ? output leave open. ? t out0 to t out15 ? output leave open. ? tstrtst schmitt-trigger a input connect this pin to v ss (in normal operation mode). ? tstvihl schmitt-trigger a input connect this pin to v ss (in normal operation mode). ? tpwr ? i/o leave open. ? notes 1. connect this pin to v dd1 or v ss depending on the mode selected. 2. input v dd1 or v ss output from the cpu to this pin depending on the mode selected. remark schmitt-trigger a : schmitt inverter schmitt-trigger b : schmitt nand schmitt-trigger c : schmitt inverter (with delay circuit)
data sheet s15726ej2v0ds 17 pd161401 5. functional description 5.1 cpu interface 5.1.1 selecting interface type the pd161401 transfers data through an 8-bit bi-directional data bus (d 7 to d 0 ), a 16-bit bi-directional data bus (d 15 to d 0 ), or a serial data input (si) pin. interface type can be selected by making the ifm1,ifm0 pin high or low, as shown in the following table. ifm1 ifm0 interface type l l serial data input l h setting prohibited h l i80 system cpu h h m68 system cpu parallel data input or serial data input can be chosen as by setting the polarity of ifm1 terminal, as shown in the following table. ifm1 /cs1, cs2 rs /rd /wr d 15 to d 8 d 7 d 6 d 5 to d 0 h: parallel input /cs1, cs2 rs /rd /wr d 15 to d 8 d 7 d 6 d 5 to d 0 l: serial input /cs1, cs2 rs note1 note1 hi-z note2 si scl hi-z note2 notes 1. fix these pins to the high or low level. 2. hi-z: high impedance 5.1.2 parallel interface when the parallel interface is selected (ifm = h), an 8-bit bi-directional data bus (d 7 to d 0 ) or 16-bit bi-directional data bus (d 15 to d 0 ) can be selected by setting the bmod flag of the control register 2 (r1) to 1 or 0. in addition, the pd161401 can be directly connected to an i80 or m68 system by making the ifm0 pin high or low as shown in the following table. ifm0 /cs1, cs2 rs /rd /wr bmod d 15 to d 8 d 7 to d 0 rs e r,/w 0 d 15 to d 8 d 7 to d 0 h: m68 system cpu /cs1, cs2 1hi-z note d 7 to d 0 rs /rd /wr 0 d 15 to d 8 d 7 to d 0 l: i80 system cpu /cs1, cs2 1hi-z note d 7 to d 0 note hi-z : high impedance (may be open)
data sheet s15726ej2v0ds 18 pd161401 the data bus signals are identified by the combination of the rs, /rd(e), /wr (r,/w) signals as shown in the following table. common m68 i80 common data bus function rs r,/w e /rd /wr bmod d 15 to d 8 d 7 to d 0 0 note1 note1 11101 1hi-zout reads the register. 0 note2 in 10110 1hi-zin writes the display data/register. 0hi-zout 01101 1hi-zout prohibited 0hi-zin 00110 1hi-zin writes the control index register. 0/1 other hi-z hi-z ? remark in : input status (cannot be open), out : output status, hi-z : high impedance (may be open) notes1. in the pd161401, the data of the display access memory register, the complementary color blink data memory register, the specified color blink data memory register and the reverse data memory access register (r12, r41, r45, r50) are read-prohibited. however, if r12 is selected, the data bus signals d 15 to d 0 enter an output state. if another register is specified, the d 15 to d 8 signals become hi-z and the d 7 to d 0 signals enter an output state. 2. only the display access memory register (r12) enters the input state. if another register is specified, the d 15 to d 8 signals become hi-z.
data sheet s15726ej2v0ds 19 pd161401 5.1.3 serial interface when the serial interface has been selected (ifm1, ifm0 = l, l), as long as the chip is in an active state (/cs1= l, cs2 = h ), serial data input (si) and serial clock input (scl) can be received. serial data is read in the order of d 7 , then d 6 to d 0 at the rising edge of the serial clock input from the serial input pin. this data is converted to parallel data in synchronization with the 8th rising edge of the serial clock. serial input data is judged as display data/command data if rs = h and an index if rs = l. the rs input is read every 8th rising edge of the serial clock after the chip becomes active and is used for data discrimination. figure 5 ? ? ? ? 1. serial interface signal chart d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 123456789101112131415161718 /cs1 si scl rs cs2 = "h" remarks 1. if the chip is not in an active state, the shift register and counter are reset to their initial statuses. 2. the serial clock counter is reset by initialization from the /disp pin. 3. data cannot be read when using serial interface mode. 4. care must be taken when performing scl wiring to avoid effects from terminal radiation or external noise caused by the wiring length. it is recommended to confirm operation using the actual equipment to be used. 5.1.4 chip select the pd161401 has chip select pins (/cs1 and cs2). the cpu parallel interface or serial interface can be used only when /cs1 = l (cs2 = h). if the chip select pins are not active, the d 0 to d 15 pins go into a high-impedance state, and the rs, /rd, and /wr pins do not become active. 5.1.5 accessing display data ram and internal registers when the cpu accesses the pd161401, the cpu only has to satisfy the requirement of the cycle time (t cyc ) and can transfer data at high speeds. usually, it is not necessary for the cpu to take wait time into consideration. when the cpu writes data to the pd161401, no dummy data is necessary. when reading data, dummy data is not necessary either. in the pd161401, the data of the display access memory register, the complementary color blink data memory register, the specified color blink data memory register and the reverse data memory access register (r12, r41, r45, r50) cannot be read. figure 5 ? ? ? ? 2 illustrates as follows.
data sheet s15726ej2v0ds 20 pd161401 figure 5 ? ? ? ? 2. writing and reading writing /wr data n n+1 n+2 n+3 reading (other than display memory access register) /wr /rd data irn irn data irn + 1 irn+1 data ir address set #n irn register data read ir address set #n+1 irn+1 register data read caution display access memory register, the complementary color blink data memory register, the specified color blink data memory register and the reverse data memory access register (r12, r41, r45, r50) cannot be read.
data sheet s15726ej2v0ds 21 pd161401 5.2 display data ram 5.2.1 display data ram this ram stores dot data for display and consists of (101 80) 8 bits. any address of this ram can be accessed by specifying an x address and a y address. display data d 0 to d 15 transmitted from the cpu corresponds to the pixels on the lcd (refer to table 5 ? ? ? ? 1 ). if the pd161401 is used in a multi-chip configuration, restrictions on display data transfer are relaxed and display setting can be performed relatively freely. the cpu writes data to the display ram via i/o buffers. this write operation is performed independently of an operation to read signals for driving the lcd. therefore, even if the display data ram is asynchronously accessed, adverse effects such as flickering do not occur or the current lcd screen. table 5 ? ? ? ? 1. display data ram msb lsb msb lsb d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dot (r) dot (g) dot (b) dot (r) dot (g) dot (b) pixel 1 pixel 2 lcd panel pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 00h 01h 02h 03h 04h 05h 06h 07h 5.2.2 x address circuit an x address of the display data ram is specified by using the x address register (r4) as shown in figure 5 ? ? ? ? 5 . if the x address increment mode (inc = 0: control register 2 (r1)) is used, the specified x address is incremented or decremented by one each time display data is written. whether the address is incremented or decremented is specified by the xdir flag of control register 2 (r1) as shown in table 5 ? ? ? ? 2 . in the increment mode, the x address is incremented up to 64h. if more display data is written, the y address is incremented (ydir = 0) or decremented (ydir = 1), and the x address returns to 00h. in the decrement mode, the x address is decremented to 00h. if more display data is written, the y address is incremented (ydir = 0) or decremented (ydir = 1), and the x address returns to 64h. when the 16-bit data bus is selected (bmod = 0), only an even address can be specified. moreover, when the 16-bit data bus is selected, dummy data is required as shown in figure 5 ? ? ? ? 3 .
data sheet s15726ej2v0ds 22 pd161401 figure 5 ? ? ? ? 3. about dummy data required when the 16-bit data bus is selected when an adc = 0 00h 01h pixel 1 pixel 101 seg 1 seg 303 pixel1 101 64h d 7 d 0 d 15 d 8 x address dummy data when an adc = 1 00h 01h pixel 1 pixel 101 seg 1 seg 303 pixel1 101 64h d 7 d 0 d 15 d 8 dummy data x address
data sheet s15726ej2v0ds 23 pd161401 5.2.3 y address circuit a y address of the display data ram is specified by using the y address register (r5) as shown in figure 5 ? ? ? ? 5 . if the y address increment mode (inc = 1: control register 2 (r1)) is used, the specified y address is incremented or decremented by one each time display is written. whether the address is incremented or decremented is specified by the ydir flag of control register 2 (r1) as shown in table 5 ? ? ? ? 2 . in the increment mode, the y address is incremented up to 4fh. if more display data is written, the x address is incremented (xdir = 0) or decremented (xdir = 1), and the y address returns to 00h. in the decrement mode, the y address is decremented to 00h. if more display data is written, the x address is incremented (xdir = 0) or decremented (xdir = 1), and the y address returns to 4fh. the relationship between the setting of inc, xdir, and ydir of control register 2 (r1) and the address is as follows: table 5 ? ? ? ? 2. relationship between inc, xdir, and ydir, and address inc setting 0 the address is successively incremented or decremented in the x direction when data is accessed. 1 the address is successively incremented or decremented in the y direction when data is accessed note . note this setting cannot be used when the 16-bit parallel interface is used. xdir setting 0 increments the x address (+1) when data is accessed. 1 decrements the x address ( ? 1) when data is accessed. ydir setting 0 increments the y address (+1) when data is accessed. 1 decrements the y address ( ? 1) when data is accessed. table 5 ? ? ? ? 3. combination of inc, xdir, and ydir, and address direction inc xdir ydir image of address scanning 00 a-1 01 a-2 10 a-3 0 11 a-4 00 b-1 01 b-2 10 b-3 1 11 b-4 caution if the access direction is changed by using inc, xdir, or ydir, be sure to set the x address register (r4) and y address register (r5) before accessing the display ram.
data sheet s15726ej2v0ds 24 pd161401 y address register (r5) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ya6 ya5 ya4 ya3 ya2 ya1 ya0 ya6 to ya0 sets a line address. figure 5 ? ? ? ? 4. combination of inc, xdir, and ydir, and address scanning image 00h 64h 00h 4fh 00h 64h 00h 4fh a-1 b-1 b-2 b-3 b-4 a-2 a-3 a-4 x address x address y address y address 5.2.4 column address circuit when the contents of the display data ram are displayed, column addresses are output to the seg output pins as shown in figure 5 ? ? ? ? 5 . the correspondence relationship between the column addresses of the display ram and segment outputs can be reversed by the adc flag (segment driver direction select flag) of control register 1 (r0). this reduces the restrictions on chip layout when the lcd module is assembled. table 5 ? ? ? ? 4. relationship between column address of display ram and segment output seg output seg 1 seg 303 0 000h column address 12eh adc (d 1 ) 1 12eh column address 000h
data sheet s15726ej2v0ds 25 pd161401 5.2.5 common scan circuit the common scan circuit sets the sequence for the scan line of the common signal in which the display ram is to be read. the ram line reading direction is set as shown in table 5 ? ? ? ? 5 by the comr flag of control register 1 (r0). for example, if the duty ratio is 1/64, the number of scroll steps is 0, and comr = 0, the ram line reading direction is from 00h to 3fh. if comr = 1, it is from 3fh to 00h. table 5 ? ? ? ? 5. relationship between common scan circuit and scan direction 0 00h 4fh comr (d 0 ) 14fh 00h in addition, scanning of the common outputs can be assigned by using the com scanning address setting register (r21) as shown in table 5 ? ? ? ? 6 , so that the scanning can be started from any o 1 to o 80 output pin. therefore, the common wiring of the lcd panel can be optimized when any duty ratio is selected. when comr = 0, the scan start (com 1 ) pin and scan end (com a ) pin are the on and o( n+a ? 1 ) pins, respectively. the value of a is 64, 72, and 80 for 1/64 duty, 1/72 duty, and 1/80 duty, respectively. when comr = 1, the scan start (com 1 ) pin and scan end (com a ) pin are the o( 82 ? a ? n ) and o( 80 ? ? ? ? n+1 ) pins, respectively. examples of com scan address settings for 1/64 duty, 1/72 duty, and 1/80 duty are shown in tables 5 ? ? ? ? 5, 5 ? ? ? ? 7 , and 5 ? ? ? ? 8 , respectively. table 5 ? ? ? ? 6. com scanning address setting (1/64 duty) comr = 0 comr = 1 the scan start (com 1 ) pin the scan end (com a ) note pin the scan start (com 1 ) pin the scan end (com a ) note pin csa4 csa3 csa2 csa1 csa0 n o n o( n+a-1 ) note o( 82-a-n ) note o( 80-n+1 ) 000001 o 1 o 64 o 17 o 80 000012 o 2 o 65 o 16 o 79 000103 o 3 o 66 o 15 o 78 000114 o 4 o 67 o 14 o 77 001005 o 5 o 68 o 13 o 76 001016 o 6 o 69 o 12 o 75 001107 o 7 o 70 o 11 o 74 001118 o 8 o 71 o 10 o 73 010009 o 9 o 72 o 9 o 72 0100110 o 10 o 73 o 8 o 71 0101011 o 11 o 74 o 7 o 70 0101112 o 12 o 75 o 6 o 69 0110013 o 13 o 76 o 5 o 68 0110114 o 14 o 77 o 4 o 67 0111015 o 15 o 78 o 3 o 66 0111116 o 16 o 79 o 2 o 65 1000017 o 17 o 80 o 1 o 64 note when in 1/64 duty, a = 64.
data sheet s15726ej2v0ds 26 pd161401 table 5 ? ? ? ? 7. com scanning address setting (1/72 duty) comr = 0 comr = 1 remark csa4 csa3 csa2 csa1 csa0 n the scan start (com 1 ) pin the scan end (com a ) note pin the scan start (com 1 ) pin the scan end (com a ) note pin o n o( n+a-1 ) note o( 82-a-n ) note o( 80-n+1 ) 000001 o 1 o 72 o 9 o 80 000012 o 2 o 73 o 8 o 79 000103 o 3 o 74 o 7 o 78 000114 o 4 o 75 o 6 o 77 001005 o 5 o 76 o 5 o 76 001016 o 6 o 77 o 4 o 75 001107 o 7 o 78 o 3 o 74 001118 o 8 o 79 o 2 o 73 010009 o 9 o 80 o 1 o 72 0100110 prohibit since here note when in 1/72 duty, a = 72 caution the com scan address setting register (r21) should be set so that o 1 scan start pin and scan end pin o 80 . if any other settings are made the ic operation is not guaranteed. table 5 ? ? ? ? 8. com scanning address setting (1/80 duty) comr = 0 comr = 1 remark csa4 csa3 csa2 csa1 csa0 n the scan start (com 1 ) pin the scan end (com a ) note pin the scan start (com 1 ) pin the scan end (com a ) note pin o n o( n+a-1 ) note o( 82-a-n ) note o( 80-n+1 ) 0000 01 o 1 o 80 o 1 o 80 0000 12 prohibit since here note when in 1/80 duty, a = 80 caution when this pd161401 is used in 1/80 duty, the com scan address setting register (r21) should be set to csa4, csa3, csa2, csa1, csa0 = 0, 0, 0, 0, 0. if any other settings are made the ic operation is not guaranteed.
data sheet s15726ej2v0ds 27 pd161401 figure 5 ? ? ? ? 5. configuration of x address register line address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 20 com 60 com 61 com 62 com 63 com 64 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0 0 1 0 0 64h d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 0 0 0 0 0 1 01h d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 0 0 0 0 0 0 00h d 6 d 5 d 4 d 3 d 2 d 1 d 0 data seg seg seg seg seg seg seg seg seg 1 2 3 3 2 1 4 5 6 303 303 302 301 302 301 300 299 298 lcd output 0 d1 1 d1 adc column address o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 comr = 0 n = 1(csa4 to csa0 = 0) o 11 o 12 o 13 o 14 o 15 o 16 o 17 o 18 o 19 o 20 o 60 o 61 o 62 o 63 o 64 setting example 1/64 duty panel pin com output x address driver: on
data sheet s15726ej2v0ds 28 pd161401 5.2.6 display data latch circuit the display data latch circuit temporarily stores (latches) the display data that is output from the display data ram to the lcd driver circuit. the display scan command for forwarding or reversing data and the display on/off command control the latched data and do not affect the data of the display data ram. 5.2.7 arbitrary address area access (window access mode (was)) with the pd161401, any area of the display ram selected by the min. ? x/y address registers (r7 and r9) and max. ? x/y address registers (r8 and r10) can be accessed. first, select the area to be accessed by using the min. ? x/y address registers and max. ? x/y address registers. when was of control register 1 is set to 1, the window access mode is then selected. the address scanning setting by inc, xdir, and ydir of control register 2 (r1) is also valid in this mode, in the same manner as when data is normally written to the display ram. in addition, data can be written from any address by specifying the x address register (r4) and y address register (r5). note that the display ram must be accessed after setting the x address register (r6) and y address register (r7) if the window access area has been set or changed by the min. ? x/y address register (r7, r9) or max. ? x/y address register (r8, r10). figure 5 ? ? ? ? 6. example of incrementing address when inc = 0, xdir = 0, and ydir = 0 start point end point 4fh 00h 64h 00h min. x address . min. y address . max. y address . max. x address . . . . cautions 1. when using the window access mode, the relationship between the start point and end point shown in the table below must be established. item address relation ship x address 00h min. ? x address x address (r4) max. ? x address 64h y address 00h min. ? y address y address (r5) max. ? y address 4fh 2. if invalid address data is set as the min./max. ? ?? ? address, operation is not guaranteed. 3. access the display ram after setting the x address register (r6) and y address register (r7) if the window access area has been set or changed by the min. ? ? ? ? x/y address register (r7, r9) or max. ? ? ? ? x/y address register (r8, r10).
data sheet s15726ej2v0ds 29 pd161401 figure 5 ? ? ? ? 7. example of sequence in window access mode no control register 2 min. data writing complete? sets start point. ye s (was = 1) sets end point. sets window access mode. . x address register (r7) min. . y address register (r9) max. . x address register (r8) max. . y address register (r10) x address register (r4) y address register (r5) display memory access register (r12) start end
data sheet s15726ej2v0ds 30 pd161401 5.3 screen processing 5.3.1 blink/reverse display circuit the pd161401 can blink or reverse a specific area of the full-dot display. blinking is to turn on/off display repeatedly at about 1 hz (complementary color or specified color can be selected) and reversing is to reverse the grayscale data on the display. the area to be blinked is specified by using the complementary color/specified color blink start/end line address registers (r39, r40, r43, and r44), complementary color/specified color blink x address registers (r38, r42), and complementary color/specified color blink data memory registers (r41, r45). first, select a blink display start line address and end line address by using the start/end line address registers. next, select the column to be blinked by using the blink x address register and blink data memory register. the specified color blink is blinked between the graphic data and the color data specified by the specified color setting register (r46). to select an area to be reversed, use the reverse start/end line address registers (r48, r49), reverse x address register (r47), and reverse data memory access register (r50). first, select line addresses at which reverse display is started and stopped, by using the reverse start/end line address registers. next, select a column to be reversed, by using the reverse x address register and reverse data memory access register. the specified blink/reverse x address is incremented by one each time blink/reverse data has been input. the complementary color/specified color blink ram and reverse ram store the data to be blinked and reversed. each ram is configured of 101 bits (12 8 + 5 bits). to access a desired bit, specify an x address. blink/reverse data d 0 to d 7 transmitted from the cpu corresponds to seg x on the lcd, as illustrated in figure 5 ? ? ? ? 8 . if the bld bit and inv bit of the blink/reverse setting register (r37) are set to h after an area and data have been set, blinking or reversing the data is started. figure 5 ? ? ? ? 9 shows the relationship between the start line address, end line address, blinking/reversing data, and lcd. if the same area is specified for complementary color blinking and specified color blinking, the specified color blinking takes precedence. table 5 ? ? ? ? 9. reversing operation and display original grayscale after reversing (supplement color) r/g display data 0, 0, 0 1, 1, 1 0, 0, 1 1, 1, 0 0, 1, 0 1, 0, 1 0, 1, 1 1, 0, 0 1, 0, 0 0, 1, 1 1, 0, 1 0, 1, 0 1, 1, 0 0, 0, 1 1, 1, 1 0, 0, 0 b display data 0, 0 1, 1 0, 1 1, 0 1, 0 0, 1 1, 1 0, 0
data sheet s15726ej2v0ds 31 pd161401 figure 5 ? ? ? ? 8. correspondence between blink/reverse data and segment when an adc = 0 d 3 d 2 d 1 d 0 data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 00h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 01h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 0 0ch r38,r42,r47 x address pixel1 pixel2 pixel3 pixel4 pixel5 pixel6 pixel7 pixel8 pixel9 pixel10 pixel11 pixel12 pixel13 pixel14 pixel15 pixel16 pixel97 pixel98 pixel99 pixel100 pixel101 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 60 61 62 63 64 note note note column output lcd output note the value written in d 2 to d 0 of x address 0ch is invalid. when an adc = 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 00h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 01h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 0 0ch pixel1 pixel2 pixel3 pixel4 pixel5 pixel6 pixel7 pixel8 pixel9 pixel10 pixel11 pixel12 pixel13 pixel14 pixel15 pixel16 pixel97 pixel98 pixel99 pixel100 pixel101 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 60 61 62 63 64 d 3 d 2 d 1 d 0 data r38,r42,r47 x address column output lcd output note the value written in d 7 to d 5 of x address 00h is invalid. figure 5 ? ? ? ? 9. blink/reverse display area setting image 0 blink/reverse data start line end line : blink or reverse pixel n 01100100 n+1 01001100 n+2 00101000 n+3 01001100 n+4 00101000 n+5 01100100 n+6 01100100 n+7 0010100
data sheet s15726ej2v0ds 32 pd161401 figure 5 ? ? ? ? 10. example of sequence of setting blink/reverse display blink/reverse start line address register data writing complete ? yes no blink/reverse end line address register blink/reverse x address register blink/reverse data memory blink/reverse setting register (r37) (bldn, inv = h) end start the data configuration of the range specification registers (start/end line address registers r39, r40, r43, r44, r48, and r49) of each line is in the format shown below. each display area is set in this format. . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x_6 x_5 x_4 x_3 x_2 x_1 x_0 x_6 to x_0 sets start/end line addresses. remark x_: cbs, cbe, sbs, sbe, ivs, ive
data sheet s15726ej2v0ds 33 pd161401 5.3.2 example of setting blink area this section explains how to specify an area to be blinked, taking complementary color blinking as an example. the same setting is also applied to specified color blinking and reverse display. (1) example of using 1 chip at duty ratio of 1/80 t.b.d. remark t.b.d. (to be determined.) (2) example of using 2 chip (master and slave) at duty ratio of 1/80 t.b.d. 5.4 oscillator the pd161401 has a cr oscillator (with external r) for main duty/sub-duty display. this oscillator generates the display clock. this oscillator is controlled by the dty flag of control register 2 (r1), and the configuration of its display clock can be set in accordance with the system used. the function of each circuit of the oscillator is shown below. the main duty display/sub-duty display oscillator becomes valid only when oscillation resistors (rm and rs) are connected to it. the clock for main duty display or sub- duty display can be selected depending on the status of the dty flag of control register 2 (r1). figure 5 ? ? ? ? 11. oscillator block osc in1 osc sync osc out osc in2 selected by dty oscillator for main duty/sub-duty to graphic driver circuit the relationship between the frame frequency (f frame ) in the normal display mode, oscillation frequency (f oscinn ), and set duty frame is as follows. f frame = f oscinn 16 n n = duty ratio
data sheet s15726ej2v0ds 34 pd161401 table 5 ? ? ? ? 10 shows the relationship between oscillation resistors rm and rs, and the display clock circuit. table 5 ? ? ? ? 10. relationship between display clock circuit, pins, and resistor rm connection rs connection clock for main duty display clock for sub-duty display example connected connected internal oscillation internal oscillation a not connected not connected external clock external clock b figure 5 ? ? ? ? 12. example of using clock osc in1 r m r s osc out osc in2 (a) (b) open f m osc in1 osc out osc in2 f s osc in1 : for main duty osc in2 : for sub-duty figure 5 ? ? ? ? 13. example of master/slave connection osc sync osc in1 osc in2 osc out open master (m,/s = h) slave (m,/s = l) (a)
data sheet s15726ej2v0ds 35 pd161401 5.5 display timing generator the display timing generator generates timing signals for the line address circuit and display data latch circuit, from the display clock. the display data is latched to the display data latch circuit in synchronization with the display clock and output to the segment driver output pins. the display data can be read completely independently of the access to the display data ram by the cpu. therefore, even if the display data ram is asynchronously accessed, no adverse effect, such as flickering, occurs on the lcd. the internal common timing, lcd ac signal (fr), and frame synchronization signal (fr sync ) are generated by the display clock. a driver waveform in the frame ac driving mode shown in figure 5 ? ? ? ? 14 is generated for the lcd driver circuit. when the pd161401 is used in a multi-chip configuration, the display timing signals for the slave chip (fr and fr sync ) must be supplied from the master chip. table 5 ? ? ? ? 11. relationship between fr, fr sync , and operation mode operation mode fr fr sync master (m,/s = h) output output slave (m,/s = l) input input
data sheet s15726ej2v0ds 36 pd161401 figure 5 ? ? ? ? 14. driver waveform in frame ac driver mode 1 frame 1 2 3 787980 45678 1 2 3 787980 45678 v lcd v lc1 v lc2 v lc3 seg 1 v lc4 v ss v lcd v lc1 v lc2 v lc3 com 1 v lc4 v ss v lcd v lc1 v lc2 v lc3 com 2 v lc4 v ss v lcd v lc1 v lc2 v lc3 com 80 v lc4 v ss ram data fr osc sync fr sync
data sheet s15726ej2v0ds 37 pd161401 5.6 power supply circuit 5.6.1 power supply circuit the power supply circuit generates the voltage necessary for driving the lcd. the power circuit consists of a booster circuit, voltage regulator circuit, and voltage follower circuit. power system control register 1 (r52) turns on/off the transformer, reference voltage generator, voltage regulator circuit (v regulator circuit), and voltage follower circuit (v/f circuit). part of the internal power supply function and an external power supply can be used in combination. table 5 ? ? ? ? 12 shows the functions controlled by the 4-bit data of power system control register 1 (r52). table 5 ? ? ? ? 13 shows examples of combinations of the power circuit functions. table 5 ? ? ? ? 12. function of each bit of power system control register status item 10 op3 : booster circuit control bit on off op2 : reference voltage generator control bit on off op1 : voltage regulator circuit (v regulator circuit) control bit on off op0 : voltage follower circuit (v/f circuit) control bit on off table 5 ? ? ? ? 13. examples of combinations (reference values) status op3 op2 op1 op0 booster circuit reference voltage v regulator circuit v/f circuit external power input booster system pins <1> only internal power supply is used 1111 ? ? v dd2 used <2> external v out power supply 0 1 1 1 ? v dd2, v out open <3> only v/f circuit is used 1 0 0 1 ? v dd2, amp out used <4> only external power supply is used 0000 v dd2, v out , v lcd , v lc1 to v lc4 open remarks 1. the ?booster system pins? are the c 1 + , c 1 ? to c 5 + , c 5 ? pins. 2. all the power circuits are turned off when the pd161401 serves as a slave (m,/s pin = l). 5.6.2 booster circuit the power supply circuit has an internal booster circuit that increases the lcd driver voltage two- to seven-fold. because this booster circuit uses the internal oscillator signals, either the oscillator must be operating or an external display clock must be input to operate this circuit. the booster circuit usually uses the c 1 + , c 1 ? to c 5 + , c 5 ? pins and v dd2 pins. keep the wiring impedance of these pins as low as possible. the number of boosting steps for main duty display and sub-duty display is set as shown in table 5 ? ? ? ? 14 by the mbt n and sbt n flags of power system control register 4 (r55). for the number of boosting steps and how to connect capacitors, refer to figure 5 ? ? ? ? 15 .
data sheet s15726ej2v0ds 38 pd161401 figure 5 ? ? ? ? 15. number of boosting steps and capacitor connection x7 x2 x2 x2 x2 open x6 x2 x2 x2 open x5 x2 x2 x2 open x4 x2 x2 open x3 x2 x2 open x2 x2 c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out c 1 + c 1 - c 2 - c 3 + c 2 + c 3 - c 4 + c 4 - c 5 + c 5 - v out2 v out to boost lcd drive voltage seven-fold to boost lcd drive voltage six-fold to boost lcd drive voltage five-fold to boost lcd drive voltage four-fold to boost lcd drive voltage three-fold to boost lcd drive voltage two-fold remark ?xn? (n = 2 to 7) of the capacitors in the above figure indicates the maximum voltage applied to the capacitors. xn : v dd2 x n (v) table 5 ? ? ? ? 14. number of boosting steps of main duty/sub-duty display booster circuit (during normal display) mbt2 mbt1 mbt0 sbt2 sbt1 sbt0 number of boosting steps (unit: fold) 000 two 0 0 1 three 0 1 0 four 011 five 100 six 1 0 1 seven 1 1 0 prohibited 1 1 1 prohibited
data sheet s15726ej2v0ds 39 pd161401 5.6.3 voltage regulator circuit the boosted voltage from v out is supplied to the voltage regulator circuit and output to the lcd drive voltage pin v lcd . because the pd161401 has a 128-step electronic volume function and an internal v lcd adjuster resistor, a high- accuracy voltage regulator circuit can be configured by adding only a few components. v lcd regulator circuit (a) when internal resistor for adjusting v lcd is used by using the internal resistor for adjusting v lcd and the electronic control function, lcd drive voltage v lcd can be controlled and the contrast of the lcd can be adjusted by using commands. in this case, no external resistor is necessary. where v lcd < v out , the value of v lcd can be calculated as follows: example calculating value of v lcd (where v lcd < v out ) v lcd = (1 + ) v ev v lcd = (1 + ) (1 ? ) v reg remark v ev = (1 ? ) v reg figure 5 ? ? ? ? 16. example of circuit using internal resistor for adjustment v lcd v ev (constant power supply + electronic volume) v lcd + ? v reg is the internal fixed power source of the ic and has three types of temperature characteristic curves. these temperature characteristic curves can be adjusted as shown in table 5 ? ? ? ? 15 depending on the setting of power system control register 1 (r52) (tcs2 to tcs0). table 5 ? ? ? ? 15 shows v reg at t a = 25 c. table 5 ? ? ? ? 15. adjusting temperature characteristic curve status tcs2 tcs1 tcs0 temperature gradient (unit: %/ c) v reg (typ.) (unit: v) internal power supply 0 0 0 ? 0.12 1.77 001 ? 0.13 1.69 010 ? 0.15 1.63 011 ? 0.17 1.59 when external reference power supply is used 1 ? ? ra rb ra rb 256 256
data sheet s15726ej2v0ds 40 pd161401 is the value of the electronic volume register. it can take any of 128 values in accordance with the data set to the 7- bit electronic control register. the value of set by the main electronic volume register (r57) (main duty display) and sub-electronic volume register (r58) (sub-duty display) is shown in table 5 ? ? ? ? 16 . table 5 ? ? ? ? 16. changes in value of depending on setting of electronic volume register mev6 mev5 mev4 mev3 mev2 mev1 mev0 sev6 sev5 sev4 sev3 sev2 sev1 sev0 0000000 256 0000001 126 0000010 125 0000011 124 1111101 2 1111110 1 1111111 0 rb/ra is a ratio of the internal resistors for adjusting v lcd . this resistance ratio can be adjusted in 128 steps, by using power control register 2 (r53) (vrrn: main duty display mode, and svrn: sub-duty display mode). the value of the reference voltage (1 + rb/ra) is determined as shown in table 5 ? ? ? ? 17 , depending on the setting of 4 bits of the v lcd internal resistance ratio register. table 5 ? ? ? ? 17. determining reference voltage value by setting of internal resistance ratio register register vrr3 vrr2 vrr1 vrr0 svr3 svr2 svr1 svr0 1 + rb/ra 0000 3 0001 4 0010 5 0011 6 0100 7 0101 8 0110 9 0111 10 1000 11 1001 12 1010 13 1011 14 1100 15 1101 16 1110 17 1111 18
data sheet s15726ej2v0ds 41 pd161401 (b) when external resistor is used (when internal resistor for adjusting v lcd is not used) lcd drive voltage v lcd can be controlled not only by a setting of the internal resistor for adjusting v lcd (irs = l) but also by connecting resistors rae, rbe, and rce between v ss and v r , between v r and amp outm , and between v r and amp outs , respectively. in this case also, lcd drive voltage v lcd and the contrast of the lcd can be adjusted by using the electronic control function and commands. in addition, the pd161401 can select two values of v lcd for normal display and partial display. these values are set by using an external divider resistor and automatically selected by the dty flag of control register 2 (r1). where v lcd < v out , the value of v lcd can be calculated by the expression in example 1 (dty = 0) and the expression in example 2 (dty = 1). example 1. to calculate value of v lcd (dty = 0, in main duty display mode) v lcd = (1 + ) v ev v lcd = (1 + ) (1 ? ) v reg remark v ev = (1 ? ) v reg example 2. to calculate value of v lcd (dty = 1, in sub-duty display mode) v lcd = (1 + ) v ev v lcd = (1 + ) (1 ? ) v reg remark v ev = (1 ? ) v reg figure 5 ? ? ? ? 17. example of circuit using external resistor (dty = 0) v lcd + ? rae rbe rae rbe rae rce rae rce 256 256 256 256
data sheet s15726ej2v0ds 42 pd161401 5.6.4 level voltage control by operational amplifier although the pd161401 has a power-saving power supply circuit, the display quality may be degraded if it is used to drive a high-load lcd panel. the driving capability of the segment output can be controlled as shown in table 5 ? ? ? ? 18 by lcs1 and lcs0 of power system control register 5 (r56), and the driving capability of the common outputs can be controlled as shown in table 5 ? ? ? ? 19 by lcc1 and lcc0 of the same register. by controlling the driving capability, the display quality and power consumption may be improved. determine the driving capability in accordance with the actual display status. if the display quality is not sufficiently improved in any driving mode, it will be necessary to supply the lcd drive voltage from an external power supply. in addition, the operational amplifier driving modes shown in table 5 ? ? ? ? 20 can be selected by the setting of hpm1 and hpm0, so that the wait time to stabilize the supply voltage immediately after the power has been turned on or off can be shortened. psm1 specifies whether a boosting voltage of v dd2 2 is applied to the v lc3 or v lc4 level voltage follower of (refer to table 5 ? ? ? ? 21 ). if a voltage boosted two-fold is applied to the voltage follower circuit, the current consumption may be reduced. thoroughly confirm and evaluate the v lc3 and v lc4 levels of the lcd panel with the actual system to determine whether the two-fold lcd drive voltage is to be supplied. psm0 can be used to set the current value of all the voltage follower circuits as shown in table 5 ? ? ? ? 22 . table 5 ? ? ? ? 18. setting driving capability of segment outputs (lcs1, lcs0 = 0, 0) lcs1 lcs0 segment output driving capability (unit: fold) 00 one 01 two 1 0 four 1 1 eight table 5 ? ? ? ? 19. setting driving capability of common outputs (lcs1, lcs0 = 0, 0) lcc1 lcc0 common output driving capability (unit: fold) 00 two 0 1 four 1 0 eight 1 1 sixteen table 5 ? ? ? ? 20. setting operation mode of operational amplifier hpm1 hpm0 mode setting 0 0 normal mode 0 1 power supply on mode 1 1 0 power supply off mode 1 1 power supply on mode 2
data sheet s15726ej2v0ds 43 pd161401 table 5 ? ? ? ? 21. setting of two-fold drive voltage psm1 mode setting 0 not used 1used table 5 ? ? ? ? 22. voltage follower bias current setting psm0 bias current setting (unit: fold) 0one 1two
data sheet s15726ej2v0ds 44 pd161401 5.6.5 application example of power supply circuit figure 5 ? ? ? ? 18. irs = h, [op3, op2, op1, op0] = [1, 1, 1, 1] six-fold drive voltage c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r open amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss v out2 figure 5 ? ? ? ? 19. irs = l, [op3, op2, op1, op0] = [1, 1, 1, 1] six-fold drive voltage rc ra' rb' c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss open v out2
data sheet s15726ej2v0ds 45 pd161401 figure 5 ? ? ? ? 20. irs = h, [op3, op2, op1, op0] = [0, 0, 0, 1] c 1 + c 2 + c 3 + c 4 + c 5 open + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r open amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss v out2 open figure 5 ? ? ? ? 21. irs = l, [op3, op2, op1, op0] = [0, 0, 0, 1] c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss open v out2 open open
data sheet s15726ej2v0ds 46 pd161401 figure 5 ? ? ? ? 22. irs = l, [op3, op2, op1, op0] = [0, 0, 0, 0] c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss open open v out2 open figure 5 ? ? ? ? 23. master/slave connection example 1 v dd1 v dd2 v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 m,/s v ss master slave open open m,/s c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v out v out + v out2 open v out2
data sheet s15726ej2v0ds 47 pd161401 figure 5 ? ? ? ? 24. master/slave connection example 2 c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 v out v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v rs v r amp outs amp outm v lcd v lc1 v lc2 v lc3 v lc4 v ss c 1 + c 2 + c 3 + c 4 + c 5 + c 1 - c 2 - c 3 - c 4 - c 5 - v dd1 v dd2 m,/s v ss open master slave open open m,/s v out v out2 open v out2
data sheet s15726ej2v0ds 48 pd161401 5.7 driving lcd the pd161401 has a full-dot driver. this full-dot driver can modulate grayscale, depending on the setting of the pulse widths. in this driving mode, eight r/g output grayscales and four b output grayscales are selected from a 17- stage grayscale palette, and the selected grayscales are registered to the output grayscale palette of the ic. for details, refer to table 5 ? ? ? ? 23 example of pulse width modulation output. 5.7.1 full-dot pulse modulation the pulse width modulation function of the pd161401 divides the segment pulse width of the signal for normal lcd display (16), and outputs the divided pulse width in accordance with the output timing of dots at the ratio of the grayscale palette selected by a command. figure 5 ? ? ? ? 25. full-dot pulse width modulation 2 expanded view of part 16/16 8/16 1/16 13 v lcd v lc1 v lc2 v lcd v lc1 v lc2 v lc3 v lc4 v ss v lcd v lc1 v lc2 v lc3 seg 1 com 1 v lc4 v ss 12345678 1 frame 78798012345678 787980 caution the width of the common output pulse is not modulated.
data sheet s15726ej2v0ds 49 pd161401 the pulse is output in the form of combined odd line/even line or even line/odd line output, as shown in figure 5 ? ? ? ? 26 . table 5 ? ? ? ? 23 shows the combination of the rising and falling edges of the pulse of each frame. figure 5 ? ? ? ? 26. example of pulse width modulation output of odd/even line 123456789101112 78798012345678 16/16 8/16 6/16 16/16 16/16 8/16 123 v lcd v lc1 v lc2 v lc3 v lc4 v ss 1 frame
data sheet s15726ej2v0ds 50 pd161401 table 5 ? ? ? ? 23. pulse width modulation output 1 or 2 frames 3 or 4 frames grayscale level com seg odd number seg even number seg odd number seg even number 0 2n+1 0 0 0 0 2n+2 0 0 0 0 1 2n+1 1 1 1 1 2n+2 1 1 1 1 2 2n+1 2 2 2 2 2n+2 2 2 2 2 3 2n+1 3 3 3 3 2n+2 3 3 3 3 4 2n+1 4 4 4 4 2n+2 4 4 4 4 5 2n+1 5 5 5 5 2n+2 5 5 5 5 6 2n+1 6 6 6 6 2n+2 6 6 6 6 7 2n+1 7 7 7 7 2n+2 7 7 7 7 8 2n+1 8 8 8 8 2n+2 8 8 8 8 9 2n+1 9 9 9 9 2n+2 9 9 9 9 10 2n+1 10 10 10 10 2n+2 10 10 10 10 11 2n+1 11 11 11 11 2n+2 11 11 11 11 12 2n+1 12 12 12 12 2n+2 12 12 12 12 13 2n+1 13 13 13 13 2n+2 13 13 13 13 14 2n+1 14 14 14 14 2n+2 14 14 14 14 15 2n+1 15 15 15 15 2n+2 15 15 15 15 16 2n+1 16 16 16 16 2n+2 16 16 16 16 remarks 1. n: integer of 0 to 39 2. a: pulse rises in the middle of a line output. 3. a: pulse rises at the beginning of a line output. 4. a: pwm pulse width (a/16)
data sheet s15726ej2v0ds 51 pd161401 5.7.2 grayscale palette the pd161401 has 17 levels of grayscale outputs. eight r/g output grayscales and four b output grayscales can be selected for each of main duty display and sub-duty display, by using the grayscale data registers (r65 to r104), and can be output as the grayscale outputs of the ic to r/g/b. table 5 ? ? ? ? 24. correspondence of grayscale levels of grayscale data registers set value of grayscale data register grayscale level d 4 d 3 d 2 d 1 d 0 remark level 0 00000off data level 1 00001 level 2 00010 level 3 00011 level 4 00100 level 5 00101 level 6 00110 level 7 00111 level 8 0100050% level 9 01001 level 10 01010 level 11 01011 level 12 01100 level 13 01101 level 14 01110 level 15 01111 level 16 10000 100%
data sheet s15726ej2v0ds 52 pd161401 5.7.3 setting of display size the pd161401 can set the main duty cycles in a range of 1/80, 1/72 and 1/64 duty, the sub-duty cycles in a range of 1/48, 1/40, 1/32, 1/24 and 1/16 duty. this can be done by setting mdt6 to mdt0 and sdt6 to sdt0 of the main duty setting register (r14) and sub-duty setting register (r17) as table 5 ? ? ? ? 25 and 5 ? ? ? ? 26 : table 5 ? ? ? ? 25. setting of main duty (r14) mdt6 mdt5 mdt4 mdt3 mdt2 mdt1 mdt0 duty 1001111 1/80 1000111 1/72 0111111 1/64 table 5 ? ? ? ? 26. setting of sub-duty (r17) sdt6 sdt5 sdt4 sdt3 sdt2 sdt1 sdt0 duty 0101111 1/48 0100111 1/40 0011111 1/32 0010111 1/24 0001111 1/16 5.7.4 setting of lcd n-line inversion and m-line shift during main duty display, the shift amount of the reverse position of ac driving and the reverse position of each display frame can be set by the main duty n-line inversion register (r15) and main duty m-line shift register (r16). they can also be set by the sub-duty n-line inversion register (r18) and sub-duty m-line shift register (r19) during sub-duty display. the n-line reverse cycle function can set a line to be reversed as shown in table 5 ? ? ? ? 27 , depending on the setting of mid5 to mid0 or sid5 to sid0 of the main or sub-duty n-line inversion register. the m-line shift amount of the reverse position of each display frame can be set as shown in table 5 ? ? ? ? 28 , by using msd5 to msd0 or ssd5 to ssd0 of the main or sub-duty m-line shift register. table 5 ? ? ? ? 27. setting of n-line inversion register (r15) mid5 mid4 mid3 mid2 mid1 mid0 sid5 sid4 sid3 sid2 sid1 sid0 reversed cycle 000000 1 000001 2 000010 3 000011 4 100101 38 100110 39 100111 40
data sheet s15726ej2v0ds 53 pd161401 table 5 ? ? ? ? 28. setting of m-line shift register msd5 msd4 msd3 msd2 msd1 msd0 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 reversed position shift amount 000000 0 000001 1 000010 2 000011 3 100110 38 100111 39 101000 40 make sure that the display size, reverse cycle, and shift amount of reverse position have the relationship indicated by the following expression: display size (duty) reverse cycle reverse shift amount
data sheet s15726ej2v0ds 54 pd161401 5.7.5 reverse driving between frames in the pd161401, the lcd drive waveform can be reversed and output between frames by setting the fxor flag of driving mode select register (r64), as shown in figure 5 ? ? ? ? 27 . this function is executed in combination with the reverse cycle and reverse shift functions. figure 5 ? ? ? ? 27. image of reversal between pulse width modulation frames reversal between frames not implemented (fxor = 0) frame n frame n+1 frame n+2 frame n+3 reverse cycle (r15, r18) reverse position shift amount (r16, r19) implementation of reversal between frames (fxor = 1) frame n frame n+1 frame n+2 frame n+3 reverse cycle (r15, r18) reverse position shift amount (r16, r19)
data sheet s15726ej2v0ds 55 pd161401 5.8 display mode 5.8.1 selecting display mode the pd161401 has two display modes: main duty display and sub-duty display. in each of these modes, any duty ratio can be selected and parts other than the display area can be scanned with a non-selected waveform. the display mode can be selected by using the dty flag of control register 2 (r1), and parameters such as the duty ratio, bias value, and number of boosting steps are automatically selected as shown in the table below. display setting main duty display (dty = 0) sub-duty display (dty = 1) duty ratio main duty setting register (r14) sub-duty setting register (r17) n-line inversion main duty n-line inversion register (r15) sub-duty n-line inversion register (r18) m-line shift main duty m-line shift register (r16) sub-duty m-line shift register (r19) v lcd adjustment power system control register 2 (r53) vrr3 to vrr0 power system control register 2 (r53) svr3 to svr0 bias value power system control register 3 (r54) bis2 to bis0 power system control register 3 (r54) sbis2 to sbis0 number of boosting steps power system control register 4 (r55) mbt2 to mbt0 power system control register 4 (r55) sbt2 to sbt0 electronic volume main electronic volume register (r57) sub-electronic volume register (r58) grayscale data setting main r grayscale data registers (r65 to r72) main g grayscale data registers (r73 to r80) main b grayscale data registers (r81 to r84) sub r grayscale data registers (r85 to r92) sub g grayscale data registers (r93 to r100) sub b grayscale data registers (r101 to r104) when the mode is changed from the main duty display mode to the sub-duty display mode or vice versa, the display screen may be temporarily disturbed, depending on the setting of each duty mode, if electric charge remains in the smoothing capacitor connected between the lcd drive voltage pins (v lcd , v lc1 to v lc4 ) and v ss . it is recommended that the following power sequence be observed to avoid any trouble that may occur when the display mode is changed.
data sheet s15726ej2v0ds 56 pd161401 (1) main duty display mode to sub-duty display mode operation status main duty display mode control register 1 disp = 0, halt = 0 r0 display off . internal operation starts. power system control register 5 (hpm1 = 1, hpm0 = 0) r56 change the operation mode of the operational amplifier to ?power off mode?. control register 2 dty = 1 r1 sub-duty display mode setting note1 wait time 1 wait for at least 50 ms. note2 power system control register 5 (hpm1 = 0, hpm0 = 1) r56 change the operation mode of the operational amplifier to ?power on mode?. wait time 2 wait for at least 150 ms. note2 power system control register 5 (hpm1 = 0, hpm0 = 0) r56 the operation mode of the operational amplifier: ?normal mode?. control register 1 (disp = 1, halt = 0) r0 display on. internal operation starts . setting completed notes 1. a scroll function cannot be used in sub-duty display mode. in the state where the scroll function is used by main duty display mode when it changes to sub-duty, a scroll function is disregarded. then, when it changes to main duty display mode again, a scroll function returns to an effective state (state before changing to sub-duty). 2. the wait times 1, 2 vary depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine these values after thorough evaluation with the actual system.
data sheet s15726ej2v0ds 57 pd161401 (2) sub-duty display mode to main duty display mode operation status sub-duty display mode note1 control register 1 disp = 0, halt = 0 r0 display off . internal operation starts. power system control register 5 (hpm1 = 0, hpm0 = 1) r56 change the operation mode of the operational amplifier to ?power on mode?. control register 2 dty = 0 r1 main duty display mode setting wait time wait for at least 160 ms. note2 power system control register 5 (hpm1 = 0, hpm0 = 0) r56 the operation mode of the operational amplifier: ?normal mode?. control register 1 (disp = 1, halt = 0) r0 display on. internal operation starts. setting completed notes 1. a scroll function cannot be used in sub-duty display mode. in the state where the scroll function is used by main duty display mode when it changes to sub-duty, a scroll function is disregarded. then, when it changes to main duty display mode again, a scroll function returns to an effective state (state before changing to sub-duty). 2. the wait time varies depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system.
data sheet s15726ej2v0ds 58 pd161401 5.8.2 screen scrolling the pd161401 has a screen scroll function. this function is enabled during main duty display. the width of the area to be fixed is specified by the scroll fixed area width register (r27) and the number of scroll steps is set by the scroll step number register (r31). by these settings, other parts of screen can be scrolled with part of the screen fixed. to specify the position of the area to be fixed, set the fixahl flag of the scroll fixed area position register (r23) as shown in table 5 ? ? ? ? 29 . specify the fixed area position on the upper part of the lcd panel in master mode and on the bottom part of the panel in slave mode. table 5 ? ? ? ? 29. scroll fixed area width register (r27) fixaw1 fixaw0 fixed area width 00 0 01 16 10 24 11 32 table 5 ? ? ? ? 30. scroll step count register (r31) mst6 mst5 mst4 mst3 mst2 mst1 mst0 number of scroll steps 0000000 0 0000001 1 0000010 2 0000011 3 1001110 78 1001111 79 1010000other settings prohibited note that the relationship between the number of scroll steps and the width of the scroll fixed area needs to be set so that the following condition is set. number of scroll steps 79 ? ? ? ? width of scroll fixed area caution if values other than the above is set, the operation is not guaranteed. table 5 ? ? ? ? 31. scroll fixed area position register (r23) fixahl lcd display position 0bottom 1 upper
data sheet s15726ej2v0ds 59 pd161401 5.8.3 scroll setting examples (1) setting example 1 duty: 1/64 duty ram read direction: normal (r0:comr = 0) scroll fixed area width: 16 lines (r27: fixaw1,0 = 0,1) (a) scroll fixed position: upper (r23: fixahl = 1) (b) scroll fixed position: bottom (r23: fixahl = 0) y address fixed area 00h 0fh display ram 3fh 4fh y address 00h display ram 30h 3fh 4fh com1 com16 com49 com64 fixed area the relationships between the numbers of scroll steps and ram y address scan order in cases of (a) and (b) are as follows. (a) number of scroll steps: 0 (r31: mstn = 00h) ram y address: 00h 0fh, 10h 3fh number of scroll steps: 1 (r31: mstn = 01h) ram y address: 00h 0fh, 11h 40h number of scroll steps: 10 (r31: mstn = 0ah) ram y address: 00h 0fh, 1ah 49h (b) number of scroll steps: 0 (r31: mstn = 00h) ram y address: 00h 2fh, 30h 3fh number of scroll steps: 1 (r31: mstn = 01h) ram y address: 00h 2fh, 40h, 30h 3fh number of scroll steps: 10 (r31: mstn = 0ah) ram y address: 0ah 2fh, 40h 49h, 30h 3fh
data sheet s15726ej2v0ds 60 pd161401 (2) setting example 2 duty: 1/64 duty ram read direction: reverse (r0: comr = 1) scroll fixed area width: 16 lines (r27: fixaw1,0 = 0,1) (a) scroll fixed position: upper (r23: fixahl = 1) (b) scroll fixed position: bottom (r23: fixahl = 0) y address fixed area 00h 0fh display ram 3fh 4fh y address 00h display ram 30h 3fh 4fh com1 com16 com49 com64 fixed area the relationships between the numbers of scroll steps and ram y address scan order in cases of (a) and (b) are as follows. (a) number of scroll steps: 0 (r31: mstn = 00h) ram y address: 3fh 10h, 0fh 00h number of scroll steps: 1 (r31: mstn = 01h) ram y address: 40h 11h, 0fh 00h number of scroll steps: 10 (r31: mstn = 0ah) ram y address: 49h 1ah, 0fh 00h (b) number of scroll steps: 0 (r31: mstn = 00h) ram y address: 3fh 30h, 2fh 00h number of scroll steps: 1 (r31: mstn = 01h) ram y address: 3fh 30h, 40h, 2fh 01h number of scroll steps: 10 (r31: mstn = 0ah) ram y address: 3fh 30hh, 49h 40h, 2fh 0ah
data sheet s15726ej2v0ds 61 pd161401 5.9 reset when the reset command is input, the ic is initialized to the default status shown in the table below. note that initialization by using the /disp pin should be used only to prevent malfunctioning due to noise. table 5 ? ? ? ? 32. default values of registers (1/2) register reset command /disp control register 1 r0 ? (disp, tron flag only) control register 2 r1 ? x address register r4 ? y address register r5 ? min. ? x address register r7 ? max. ? x address register r8 ? min. ? y address register r9 ? min. ? y address register r10 ? display memory access register r12 main duty setting register r14 ? main duty n-line inversion register r15 ? main duty m-line shift register r16 ? sub-duty setting register r17 ? sub-duty n-line inversion register r18 ? sub-duty m-line shift register r19 ? com scanning address setting register r21 ? sub-duty start address register r22 ? scroll fixed area position register r23 ? scroll fixed area width register r27 ? scroll steps number register r31 ? blinking/reverse setting register r37 ? complementary color blink x address register r38 ? complementary color blink start line address register r39 ? complementary color blink end line address register r40 ? complementary color blink data memory register r41 specified color blink x address register r42 ? specified color blink start line address register r43 ? specified color blink end line address register r44 ? specified color blink data memory register r45 specified color setting register r46 ? reverse x address register r47 ? reverse start line address register r48 ? remark o: default value is input. x: default value is not input. cautions 1. when initialization is made using the /disp pin, the contents of memory are not guaranteed. in this case, use the initialized ram. when initialization is made via the reset command, the contents of memory are retained. 2. if the device is initialized by the /disp pin while the serial interface is being used, the serial clock counter is initialized. 3. always input the reset command as the first command after power application.
data sheet s15726ej2v0ds 62 pd161401 table 5 ? ? ? ? 32. default values of registers (2/2) register reset command /disp reverse end line address register r49 ? reversed data memory access register r50 power system control register 1 r52 ? power system control register 2 r53 ? power system control register 3 r54 ? power system control register 4 r55 ? power system control register 5 r56 ? main electronic volume register r57 ? sub-electronic volume register r58 ? ram test mode setting register r61 ? driving mode select register r64 ? main r grayscale data registers 1 to 8 r65 to r72 ? main g grayscale data registers 1 to 8 r73 to r80 ? main b grayscale data registers 1 to 4 r81 to r84 ? sub r grayscale data registers 1 to 8 r85 to r92 ? sub g grayscale data registers 1 to 8 r93 to r100 ? sub b grayscale data registers 1 to 8 r101 to r104 ? remark o: default value is input. x: default value is not input. cautions 1. when initialization is made using the /disp pin, the contents of memory are not guaranteed. in this case, use the initialized ram. when initialization is made via the reset command, the contents of memory are retained. 2. if the device is initialized by the /disp pin while the serial interface is being used, the serial clock counter is initialized. 3. always input the reset command as the first command after power application.
data sheet s15726ej2v0ds 63 pd161401 6. commands the pd161401 identifies data bus signals by a combination of the rs, /rd (e), and /wr (r,/w) signals. it interprets and executes commands only in accordance with the internal timing, without being dependent upon the external clock. therefore, the processing speed is extremely high and, usually, no busy check is necessary. an i80 system cpu interface inputs a low pulse to the /rd pin when it reads data from the pd161401 to issue a command. it inputs a low pulse to the /wr pin when it writes data to the pd161401. data can be read from an m68 system cpu interface if a high-pulse signal is input to the r,/w pin, and written if a low-pulse signal is input to the r,/w pin. a command is executed if a high-pulse signal is input to the e pin in this status. therefore, in the explanation of the commands and display commands in 6.1 control register 1 (r0) and the sections that follow, the m68 system cpu interface uses h, instead of /rd (e), when reading status or display data. this is how it differs from the i80 system cpu interface. the commands of the pd161401 are explained below, taking an i80 system cpu interface as an example. when the serial interface is used, sequentially input data to the pd161401, starting from d 7 . the data bus length to input commands is as follows: ? commands other than those that manipulate the display memory access register (r12) are input in byte units, regardless of the value of bmod (control register 2 (r1), bus length setting). ? the commands that manipulate the display memory access register (r12) are input in 1-byte units when bmod = 1, or in 2-byte units when bmod = 0. a. commands other than those that manipulate display memory access register (r12) bmod = 1 (8-bit data bus) pin d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bmod = 0 (16-bit data bus) pin d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data note note note note note note note note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0 or 1 b. display memory access register (r12) bmod = 1 (8-bit data bus) pin d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bmod = 0 (16-bit data bus) pin d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
data sheet s15726ej2v0ds 64 pd161401 6.1 control register 1 (r0) this command specifies the general operation mode of the pd161401. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 tron was comf disp stby halt adc comr tron 0: normal mode (all values written to the test register are ignored) 1: test register valid mode (values written to the test register are valid) was 0: normal data write mode 1: window access mode (refer to 5.2.7 arbitrary address area access (window access mode (was)) .) comf 0: normal display operation 1: all output from common pins is off (all the common pins output a non-selected waveform. at this time, the segment pins output off data (level 0)). disp 0: display off (all the lcd output pins output a v ss level, and the oscillator and dc/dc converter operate.) 1: display on stby 0: normal operation 1: internal operation and oscillation stop. display off halt 0: internal operation starts. 1: internal operation stops (all the lcd output pins output a v ss level, the oscillator operates, and the dc/dc converter stops, and the reference voltage generator operates). adc column addresses correspond to seg outputs that are used to display the display data ram (refer to table 6 ? ? ? ? 1 ). comr selects the direction in which the lines of the graphic ram are read (refer to table 6 ? ? ? ? 2 ). table 6 ? ? ? ? 1. relationship between column address of display ram and segment output seg output seg 1 ? ? ? seg 303 0 000h column address 12eh adc (d 1 ) 1 12eh column address 000h table 6 ? ? ? ? 2. relationship between common scan circuit and scan direction 0 00h 4fh comr (d 0 ) 14fh 00h default (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000
data sheet s15726ej2v0ds 65 pd161401 6.2 control register 2 (r1) this command specifies the general operation mode of the pd161401. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 fdm bmod dty inc xdir ydir fdm sets all screen display modes. 0: normal operation 1: all screen display (turns on all screens [outputs grayscale level 16 to all screens].) bmod selects data length when parallel data is input. 0: 16-bit data bus 1: 8-bit data bus dty 0: main duty display mode 1: sub-duty display mode inc note 0: increments/decrements x address each time it is accessed. 1: increments/decrements y address each time it is accessed. xdir note specifies the direction in which the x address is to be accessed. 0: increment (+1) 1: decrement (-1) ydir note specifies the direction in which the y address is to be accessed. 0: increment (+1) 1: decrement (-1) note if the access direction is changed by inc, xdir, or ydir, be sure to set the x address register (r4) and y address register (r5) before accessing the display ram. table 6 ? ? ? ? 3. relationship between functions of pd161401 and display mode display setting main duty display (dty = 0) sub-duty display (dty = 1) duty main duty setting register (r14) sub-duty setting register (r17) n-line inversion main duty n-line inversion register (r15) sub-duty n-line inversion register (r18) m-line shift main duty m-line shift register (r16) sub-duty m-line shift register (r19) v lcd adjustment power system control register 2 (r53) vrr3 to vrr0 power system control register 2 (r53) svr3 to svr0 bias value power system control register 3 (r54) bis2 to bis0 power system control register 3 (r54) sbis to sbis0 number of boosting steps power system control register 4 (r55) mbt2 to mbt0 power system control register 4 (r55) sbt2 to sbt0 electronic volume main electronic volume register (r57) sub-electronic volume register (r58) grayscale data setting main r grayscale data register (r65 to r72) main g grayscale data register (r73 to r80) main b grayscale data register (r81 to r84) sub r grayscale data register (r85 to r92) sub g grayscale data register (r93 to r100) sub b grayscale data register (r101 to r104) default (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 note 0 note 0000 note 0 or 1
data sheet s15726ej2v0ds 66 pd161401 6.3 reset command register (r3) when this command is input, the registers of the pd161401 (r0 to r104) are set to the default values. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 100000001 caution at power application, be sure to input the reset command as the first command. 6.4 x address register (r4) the x address register specifies the x address of the display ram the cpu accesses. this address is automatically incremented or decremented each time the display ram has been accessed (inc = 0). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 xa6 xa5 xa4 xa3 xa2 xa1 xa0 caution if the access direction is changed by control register 2 (r1: inc, xdir, ydir) or window access area is changed or set by min. ? ?? ? x address register (r7, r9) and max. ? ?? ? x address register (r8, r10), be sure to set the x address register (r4) and y address register (r5) before accessing the display ram. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.5 y address register (r5) the y address register specifies the y address of the display ram the cpu accesses. this address is automatically incremented or decremented each time the display ram is accessed (inc = 1). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ya6 ya5 ya4 ya3 ya2 ya1 ya0 ya6 to ya0 sets line address caution if the access direction is changed by control register 2 (r1: inc, xdir, ydir), be sure to set the x address register (r4) and y address register (r5) before accessing the display ram. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 67 pd161401 6.6 min. x address register (r7) this register specifies the x address of the start point of the display ram the cpu accesses when the window access mode is used. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 xmn6 xmn5 xmn4 xmn3 xmn2 xmn1 xmn0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.7 max. x address register (r8) this register specifies the x address of the end point of the display ram the cpu accesses when the window access mode is used. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 xmx6 xmx5 xmx4 xmx3 xmx2 xmx1 xmx0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.8 min. y address register (r9) this register specifies the y address of the start point of the display ram the cpu accesses when the window access mode is used. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ymn6 ymn5 ymn4 ymn3 ymn2 ymn1 ymn0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 68 pd161401 6.9 max. y address register (r10) this register specifies the y address of the end point of the display ram the cpu accesses when the window access mode is used. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ymx6 ymx5 ymx4 ymx3 ymx2 ymx1 ymx0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.10 display memory access register (r12) the display memory access register is used to access the display ram. when data is written to this register, it is directly written to the display ram. in the pd161401, the data of the display access memory register (r12) cannot be read. bmod = 1 (8-bit data bus) rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bmod = 0 (16-bit data bus) rs d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 1d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 default value (default value of reset command) bmod = 1 (8-bit data bus) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note note note 0 or 1 bmod = 0 (16-bit data bus) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 note note note note note note note note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note note note 0 or 1
data sheet s15726ej2v0ds 69 pd161401 6.11 main duty setting register (r14) this register can set the display duty ratio in a range of 1/80, 1/72 and 1/64 duty as shown in table 6 ? ? ? ? 5 in the main duty display mode. before changing the contents of this register, be sure to stop the internal operation by using the halt command (control register 1 (r0)). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 mdt6mdt5mdt4mdt3mdt2mdt1mdt0 table 6 ? ? ? ? 5. main duty setting register (r14) mdt6 mdt5 mdt4 mdt3 mdt2 mdt1 mdt0 duty 1001111 1/80 1000111 1/72 0111111 1/64 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 1001111 note 0 or 1 6.12 main duty n-line inversion register (r15) this register can set the line position of ac driving in the main duty display mode as shown in table 6 ? ? ? ? 6 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 mid5 mid4 mid3 mid2 mid1 mid0 table 6 ? ? ? ? 6. setting of main duty n-line inversion register (r15) mid5 mid4 mid3 mid2 mid1 mid0 line to be reversed 000000 1 000001 2 000010 3 100101 38 100110 39 100111 40 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note 100111 note 0 or 1
data sheet s15726ej2v0ds 70 pd161401 6.13 main duty m-line shift register (r16) this register shifts the reverse position of each frame in the main duty display mode by the shift amount shown in table 6 ? ? ? ? 7 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 msd5msd4msd3msd2msd1msd0 table 6 ? ? ? ? 7. main duty m-line shift register (r16) msd5 msd4 msd3 msd2 msd1 msd0 shift amount of position to be reversed 000000 0 000001 1 000010 2 000011 3 100110 38 100111 39 101000 40 make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows. display size (duty) reverse cycle reverse shift amount default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note 000000 note 0 or1
data sheet s15726ej2v0ds 71 pd161401 6.14 sub-duty setting register (r17) this register can set the display duty ratio in a range of 1/48, 1/40, 1/32, 1/24 and 1/16 as shown in table 6 ? ? ? ? 8 in the sub-duty display mode by setting sdt6 to sdt0. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 sdt6sdt5sdt4sdt3sdt2sdt1sdt0 table 6 ? ? ? ? 8. main duty setting register (r17) sdt6 sdt5 sdt4 sdt3 sdt2 sdt1 sdt0 duty 0101111 1/48 0100111 1/40 0011111 1/32 0010111 1/24 0001111 1/16 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0101111 note 0 or 1
data sheet s15726ej2v0ds 72 pd161401 6.15 sub-duty n-line inversion register (r18) this register can set the line position of driving in the sub-duty display mode as shown in table 6 ? ? ? ? 9 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 sid5sid4sid3sid2sid1sid0 table 6 ? ? ? ? 9. sub-duty n-line inversion register (r18) sid5 sid4 sid3 sid2 sid1 sid0 line to be reversed 000000 1 000001 2 000010 3 000011 4 100101 38 100110 39 100111 40 caution please protect the following relations. sub-duty display size (duty) sub-duty reversed line if this relation is not protected, the operation is not guaranteed. however, when the above-mentioned relation is not protected, inside pd161401, processing which makes reversed line equal to display size is carried out. in addition, the value of a register is not rewritten automatically. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note 100111 note 0 or 1
data sheet s15726ej2v0ds 73 pd161401 6.16 sub-duty m-line shift register (r19) this register shifts the reverse position of each frame in the sub-duty display mode by the shift amount shown in table 6 ? ? ? ? 10 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ssd5ssd4ssd3ssd2ssd1ssd0 table 6 ? ? ? ? 10. sub-duty m-line shift register (r19) ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 shift amount of position to be reversed 000000 0 000001 1 000010 2 000011 3 100110 38 100111 39 101000 40 make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows. display size (duty) reverse cycle reverse shift amount default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note 000000 note 0 or 1
data sheet s15726ej2v0ds 74 pd161401 6.17 com scanning address setting register (r21) this command specifies that scanning of the common outputs can be started from any of the on (n = 1 to 80) output pins. set the csa4 to csa0 bits as shown in table 6 ? ? ? ? 11 (1/2) . the scan start pin can be specified by the value n obtained from this table and the selected duty shown in table 6 ? ? ? ? 11 (2/2) . the common wiring on the lcd panel can be optimized according to the selected duty. tables 6 ? ? ? ? 12 , 6 ? ? ? ? 13 , and 6 ? ? ? ? 14 indicate examples of the com scan address settings for 1/64 duty, 1/72 duty, and 1/80 duty. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 csa4 csa3 csa2 csa1 csa0 table 6 ? ? ? ? 11. com scanning address setting register (1/2) csa4 csa3 csa2 csa1 csa0 n 00000 1 00001 2 00010 3 01110 15 01111 16 10000 17 1 0 0 0 1 other settings prohibited table 6 ? ? ? ? 11. com scanning address setting register (2/2) comr = 0 comr = 1 scanning start (com1) pin scanning end (coma) note pin scanning start (com1) pin scanning end (coma) note pin on o(n+a ? 1) note o(82 ? a ? n) o(80 ? n+1) note note a = 64: 1/64 duty a = 72: 1/72 duty a = 80: 1/80 duty caution set the com scan address setting register so that the scan start pin and scan end pin satisfy the equation below. if a value that exceeds this condition is set, the pd161401 operation is not guaranteed. o 1 scan start pin and scan end pin o 80
data sheet s15726ej2v0ds 75 pd161401 table 6 ? ? ? ? 12. example of com scanning address setting (1/64 duty) comr = 0 comr = 1 scanning start (com1) pin scanning end (coma) note pin scanning start (com1) pin scanning end (coma) note pin csa4 csa3 csa2 csa1 csa0 n on o(n+a ? 1) note o(82 ? a ? n) o(80 ? n+1) note 000001 o 1 o 64 o 17 o 80 000012 o 2 o 65 o 16 o 79 000103 o 3 o 66 o 15 o 78 000114 o 4 o 67 o 14 o 77 001005 o 5 o 68 o 13 o 76 001016 o 6 o 69 o 12 o 75 001107 o 7 o 70 o 11 o 74 001118 o 8 o 71 o 10 o 73 010009 o 9 o 72 o 9 o 72 0100110 o 10 o 73 o 8 o 71 0101011 o 11 o 74 o 7 o 70 0101112 o 12 o 75 o 6 o 69 0110013 o 13 o 76 o 5 o 68 0110114 o 14 o 77 o 4 o 67 0111015 o 15 o 78 o 3 o 66 0111116 o 16 o 79 o 2 o 65 1000017 o 17 o 80 o 1 o 64 note a = 64 at 1/64 duty
data sheet s15726ej2v0ds 76 pd161401 table 6 ? ? ? ? 13. example of com scanning address setting (1/72 duty) comr = 0 comr = 1 remark scanning start (com1) pin scanning end (coma) note pin scanning start (com1) pin scanning end (coma) note pi n csa4 csa3 csa2 csa1 csa0 n on o (n+a ? 1) note o(82 ? a ? n) o(80 ? n+1) note 000001 o 1 o 72 o 9 o 80 000012 o 2 o 73 o 8 o 79 000103 o 3 o 74 o 7 o 78 000114 o 4 o 75 o 6 o 77 001005 o 5 o 76 o 5 o 76 001016 o 6 o 77 o 4 o 75 001107 o 7 o 78 o 3 o 74 001118 o 8 o 79 o 2 o 73 010009 o 9 o 80 o 1 o 72 0100110 other settings prohibited note a = 72 at 1/72 duty caution set the com scan address setting register (r21) so that o 1 scan start pin and scan end pin o 80 . if a value that exceeds this condition is set, the pd161401 operation is not guaranteed table 6 ? ? ? ? 14. example of com scanning address setting (1/80 duty) comr = 0 comr = 1 remark scanning start (com1) pin scanning end (coma) note pin scanning start (com1) pin scanning end (coma) note pin csa4 csa3 csa2 csa1 csa0 n on o(n+a ? 1) note o(82 ? a ? n) o(80 ? n+1) note 0000 0 1 o 1 o 80 o 1 o 80 0000 1 2 other settings prohibited note a = 80 at 1/80 duty caution when the pd161401 is used in 1/80 duty, set the com scan address setting register (r21) to csa4, csa3, csa2, csa1, csa0 = 0, 0, 0, 0, 0. if any other settings are made, the pd161401 operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 77 pd161401 6.18 sub-duty start address register (r22) the sub-duty start address register specifies the start address of the display ram the cpu accesses to use the sub- duty display mode. the sub-duty display area starts from this start line address and consists of the number of lines specified by the sub-duty setting register (r17). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 table 6 ? ? ? ? 15. sub-duty start address register ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 common 0000000 com 1 0000001 com 2 0000010 com 3 0000011 com 4 1001101 com 78 1001110 com 79 1001111 com 80 make sure that ssa (r22) and sdt (r17) have in the following relationship. ssan + sdtn mdt 4fh default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 78 pd161401 6.19 scroll fixed area position register (r23) this command specifies the display position of the scroll fixed area to upper or bottom of side in lcd panel. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 fixahl table 6 ? ? ? ? 16. scroll fixed position register (r23) fixahl display position 0 bottom 1 upper default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note 1 note 0 or 1 6.20 scroll fixed area width register (r27) this register selects the width of the area to be fixed from 0, 16, 24, and 32 lines. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 fixaw1 fixaw0 table 4 ? ? ? ? 16. scroll fixed area width register (r27) fixaw1 fixaw0 fixed area width 00 0 01 16 10 24 11 32 even if the screen display size is changed by the duty setting register (r14 and r17), fixaw1 and fixaw0 are not overwritten. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note 00 note 0 or 1
data sheet s15726ej2v0ds 79 pd161401 6.21 scroll step number register (r31) this register sets the number of scroll steps when the scroll function is used. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 mst6mst5mst4mst3mst2mst1mst0 table 6 ? ? ? ? 18. scroll step number register (r31) mst6 mst5 mst4 mst3 mst2 mst1 mst0 number of scroll steps 0000000 0 0000001 1 0000010 2 0000011 3 1001101 77 1001110 78 1001111 79 1010000 other settings prohibited caution the relationship between the number of scroll steps and scroll fixed area width should be as follows. number of scroll steps 79 ? ? ? ? scroll fixed area width if values exceeding the above condition are set, the operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 80 pd161401 6.22 blink/reverse setting register (r37) this register controls blink display or reverse display. blink display is controlled by the bld1 and bld0 flags of this register, and reverse display is controlled by the inv flag, as shown in the table below. the condition of each of the blink and reverse display areas is individually set by r38 to r50. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 inv bld1 bld0 table 6 ? ? ? ? 19. blink/reverse display control inv display 0 reverse display off 1 reverse display on bld1 display 0 specified-color blink display off 1 specified-color blink display on bld0 display 0 complementary-color blink display off 1 complementary-color blink display on default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note 0 note 00 note 0 or 1 6.23 complementary color blink x address register (r38) the complementary color blink x address register specifies the x address of the complementary color blink ram the cpu accesses. this address is automatically incremented each time the complementary color blink data ram is accessed. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 cbx3 cbx2 cbx1 cbx0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note 0000 note 0 or 1
data sheet s15726ej2v0ds 81 pd161401 6.24 complementary color blink start line address register (r39) the complementary color blink start line address register specifies the start line address the cpu accesses to use complementary color blinking display. the range of the complementary color blink lines is determined by this register and the complementary color blink end line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 cbs6 cbs5 cbs4 cbs3 cbs2 cbs1 cbs0 cbs6 to cbs0 sets a start line address caution make sure that cbs [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.25 complementary color blink end line address register (r40) the complementary color blink end line address register specifies the end line address the cpu accesses to use complementary color blink display. the range of the complementary color blink lines is determined by this register and the complementary color blink start line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 cbe6 cbe5 cbe4 cbe3 cbe2 cbe1 cbe0 cbe6 to cbe0 sets an end line address caution make sure that cbe [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 82 pd161401 6.26 complementary color blink data memory register (r41) the complementary color blink data memory register is used to access the complementary color blink data ram. if this register is accessed for write, data is directly written to the complementary color blink data ram. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data status 0normal 1 complementary color blinking default value (default value of reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note note note 0 or 1 6.27 specified color blink x address register (r42) the specified color blink x address register specifies the x address of the specified color blinking ram the cpu accesses. this address is automatically incremented each time the specified color blink data ram is accessed. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 sbx3 sbx2 sbx1 sbx0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note 0000 note 0 or 1
data sheet s15726ej2v0ds 83 pd161401 6.28 specified color blink start line address register (r43) the specified color blink start line address register specifies the start line address the cpu accesses to use specified color blinking display. the range of the specified color blink lines is determined by this register and the specified color blinking end line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 sbs6 sbs5 sbs4 sbs3 sbs2 sbs1 sbs0 sbs6 to sbs0 sets a start line address. caution make sure that sbs [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.29 specified color blink end line address register (r44) the specified color blink end line address register specifies the end line address the cpu accesses to use specified color blink display. the range of the specified color blink lines is determined by this register and the specified color blink start line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 sbe6 sbe5 sbe4 sbe3 sbe2 sbe1 sbe0 sbe6 to sbe0 sets an end line address. caution make sure that sbe [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000
data sheet s15726ej2v0ds 84 pd161401 6.30 specified color blink data memory register (r45) the specified color blink data memory register is used to access the specified color blink data ram. if this register is accessed for write, data is directly written to the specified color blink data ram. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data status 0normal 1 specified color blinking default value (default value of reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note note note 0 or 1 6.31 specified color setting register (r46) this register sets specified color data when the specified color blink function is used. the data between this data and the display ram data blinks in a specified color. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 remark d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 r g b in 256-color mode default value (default value of reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 6.32 reverse x address register (r47) the reverse x address register specifies the x address of the reverse data ram the cpu accesses. this address is incremented each time the reverse ram has been accessed. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ivx3ivx2ivx1ivx0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note 0000 note 0 or 1
data sheet s15726ej2v0ds 85 pd161401 6.33 reverse start line address register (r48) the reverse start line address register specifies start line address of the display ram the cpu accesses for reverse display. the range of the reverse lines is determined by this register and the reverse end line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ivs6 ivs5 ivs4 ivs3 ivs2 ivs1 ivs0 ivs6 to ivs0 sets a start line address. caution make sure that ivs [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.34 reverse end line address register (r49) the reverse end line address register specifies the end line address of the display ram the cpu accesses for reverse display. the range of the reverse lines is determined by this register and the reverse start line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ive6 ive5 ive4 ive3 ive2 ive1 ive0 ive6 to ive0 sets an end line address. caution make sure that ive [6:0] 4fh. if 4fh is exceeded, operation is not guaranteed. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 86 pd161401 6.35 reverse data memory access register (r50) the reverse data memory access register is used to access the reverse data ram. when this register is accessed for write, data is directly written to the reverse data ram. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data status 0normal 1 reverse default value (default value of reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note note note note note 0 or 1
data sheet s15726ej2v0ds 87 pd161401 6.36 power system control register 1 (r52) this command sets the power system mode of the pd161401. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 tcs2 tcs1 tcs0 op3 op2 op1 op0 tcs2 to tcs0 these bits set the value that selects the temperature curve of the v reg voltage to a value shown in table 6 ? ? ? ? 20 . op3 to op0 these bits turn on/off the booster circuit, reference voltage generator, control the voltage regulator circuit (v regulator circuit) and voltage follower circuit (v/f circuit). the functions controlled by these four-power control set command controlled by these 4 bits are listed in table 6 ? ? ? ? 21 . table 6 ? ? ? ? 20. v reg voltage temperature curve value tcs2 tcs1 tcs0 status temperature gradient (unit: %/ c) v reg (typ.) (unit: v) 0 0 0 ?0.12 1.77 0 0 1 ?0.13 1.69 0 1 0 ?0.15 1.63 011 internal power supply ?0.17 1.59 1 x x when external reference power supply is used ?? table 6 ? ? ? ? 21. details of control by each bit of power system control register status item 10 op3 : booster circuit control bit on off op2 : reference voltage generator control bit on off op1 : voltage regulator circuit (v regulator circuit) control bit on off op0 : voltage follower circuit (v/f circuit) control bit on off default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 88 pd161401 6.37 power system control register 2 (r53) this command sets the power system mode of the pd161401. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 1 0 vrr3 vrr2 vrr1 vrr0 svr3 svr2 svr1 svr0 vrr3 to vrr0 when the main duty display mode is used, the resistance ratio can be changed in 16 steps by the v lcd internal resistance ratio adjustment command. four bits of the v lcd internal resistance ratio adjustment register set the reference value of (1 + rb/ra) to the value shown in table 6 ? ? ? ? 22 . svr3 to svr0 when the sub-duty display mode is used, the resistance ratio can be changed in 16 steps by the v lcd internal resistance ratio adjustment command. four bits of the v lcd internal resistance ratio adjustment register set the reference value of (1 + rb/ra) to the value shown in table 6 ? ? ? ? 22 . table 6-22. vlcd internal resistance ratio adjustment register register vrr3 vrr2 vrr1 vrr0 svr3 svr2 svr1 svr0 1 + rb/ra 0000 3 0001 4 0010 5 0011 6 0100 7 0101 8 0110 9 0111 10 1000 11 1001 12 1010 13 1011 14 1100 15 1101 16 1110 17 1111 18 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000
data sheet s15726ej2v0ds 89 pd161401 6.38 power system control register 3 (r54) this command sets the bias value for main duty display and sub-duty display by the pd161401. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 bis2 bis1 bis0 sbis2 sbis1 sbis0 these flags select the bias ratio in the main duty display mode as follows: bis2 bis1 bis0 bias ratio 0001/9 bias 0011/8 bias 0101/7 bias 0111/6 bias 1001/5 bias 1 0 1 prohibited 1 1 0 prohibited bis2 to bis0 note 1 1 1 prohibited these flags select the bias ratio in the sub-duty display mode as follows: sbis2 sbis1 sbis0 bias ratio 0001/9 bias 0011/8 bias 0101/7 bias 0111/6 bias 1001/5 bias 1 0 1 prohibited 1 1 0 prohibited sbis2 to sbis0 note 1 1 1 prohibited note before changing these flags, execute the halt command. default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 000 note 000 note 0 or 1
data sheet s15726ej2v0ds 90 pd161401 6.39 power system control register 4 (r55) this command sets the number of boosting steps for main duty display and sub-duty display of pd161401 as shown in table 6 ? ? ? ? 23 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 mbt2 mbt1 mbt0 sbt2 sbt1 sbt0 table 6 ? ? ? ? 23. number of boosting steps for main/sub-duty display of booster circuit mbt2 mbt1 mbt0 sbt2 sbt1 sbt0 number of boosting steps (unit: fold) 000 two 001 three 010 four 011 five 100 six 101 seven 1 1 0 prohibited 1 1 1 prohibited default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 000 note 000 note 0 or 1
data sheet s15726ej2v0ds 91 pd161401 6.40 power system control register 5 (r56) this command sets the status of the voltage follower circuit of the pd161401 that drives the lcd, as follows: rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 lcs1 lcs0 lcc1 lcc0 hpm1 hpm0 psm1 psm0 table 6 ? ? ? ? 24. setting of segment output driving capability (lcs1, lcs0 = 0, 0) lcs1 lcs0 segment output driving capability (unit: fold) 00 one 01 two 1 0 four 1 1 eight table 6 ? ? ? ? 25. setting of common output driving capability (lcs1, lcs0 = 0, 0) lcc1 lcc0 common output driving capability (unit: fold) 00 two 0 1 four 1 0 eight 1 1 sixteen table 6 ? ? ? ? 26. setting of operational amplifier operation mode hpm1 hpm0 mode setting 0 0 normal mode 0 1 power on mode1 1 0 power off mode 1 1 power on mode2 table 6 ? ? ? ? 27. setting of two-fold supply voltage (v lc3 , v lc4 level voltage follower power supply) psm1 mode setting 0 not used 1used table 6 ? ? ? ? 28. setting of voltage follower bias current psm0 bias current setting (unit: fold) 0one 1two default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00010010
data sheet s15726ej2v0ds 92 pd161401 6.41 main electronic volume register (r57) the main electronic volume register specifies the electronic volume value for adjusting the contrast in the main duty display mode, in 128 steps. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 mev6 mev5 mev4 mev3 mev2 mev1 mev0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1 6.42 sub-electronic volume register (r58) the sub-electronic volume register specifies an electronic volume value for adjusting the contrast in the sub-duty display mode, in 128 steps. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 sev6 sev5 sev4 sev3 sev2 sev1 sev0 default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note 0000000 note 0 or 1
data sheet s15726ej2v0ds 93 pd161401 6.43 ram test mode setting register (r61) the ram test mode setting register directly writes the data of each display status to the display ram as shown in table 6 ? ? ? ? 29 . rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 rts2 rts1 rts0 table 6 ? ? ? ? 29. ram test mode rts2 rts1 rts0 write data 0 0 0 normal operation 0 0 1 all [00000000] / pixel display 0 1 0 all [11111111] / pixel display 0 1 1 checker pattern display of [00000000] / [11111111] 1 0 0 vertical grayscale bar display 1 0 1 horizontal grayscale bar display 1 1 0 each color grayscale display 1 1 1 256-color display default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note note 000 note 0 or 1 6.44 driving mode select register (r64) the fxor flag of the drive mode select register controls the reversal of the lcd drive waveform between frames as shown in table 6 ? ? ? ? 30 . note that the reverse function is executed between frames regardless of the fxor flag during sub-duty display. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1fxor table 6 ? ? ? ? 30. driving mode select register (r64) fxor reversing between frames 0off 1on default value (default value of reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note note 0 note note note note 0 or 1
data sheet s15726ej2v0ds 94 pd161401 6.45 main r grayscale data registers (r65 to r72) the main r grayscale data registers specify the grayscale level of the r output in the main duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r65 0, 0, 0 1 mrg4 mrg3 mrg2 mrg1 mrg0 r66 0, 0, 1 1 mrg4 mrg3 mrg2 mrg1 mrg0 r67 0, 1, 0 1 mrg4 mrg3 mrg2 mrg1 mrg0 r68 0, 1, 1 1 mrg4 mrg3 mrg2 mrg1 mrg0 r69 1, 0, 0 1 mrg4 mrg3 mrg2 mrg1 mrg0 r70 1, 0, 1 1 mrg4 mrg3 mrg2 mrg1 mrg0 r71 1, 1, 0 1 mrg4 mrg3 mrg2 mrg1 mrg0 r72 1, 1, 1 1 mrg4 mrg3 mrg2 mrg1 mrg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 95 pd161401 6.46 main g grayscale data registers (r73 to r80) the main g grayscale data registers specify the grayscale level of the g output in the main duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r73 0, 0, 0 1 mgg4 mgg3 mgg2 mgg1 mgg0 r74 0, 0, 1 1 mgg4 mgg3 mgg2 mgg1 mgg0 r75 0, 1, 0 1 mgg4 mgg3 mgg2 mgg1 mgg0 r76 0, 1, 1 1 mgg4 mgg3 mgg2 mgg1 mgg0 r77 1, 0, 0 1 mgg4 mgg3 mgg2 mgg1 mgg0 r78 1, 0, 1 1 mgg4 mgg3 mgg2 mgg1 mgg0 r79 1, 1, 0 1 mgg4 mgg3 mgg2 mgg1 mgg0 r80 1, 1, 1 1 mgg4 mgg3 mgg2 mgg1 mgg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 96 pd161401 6.47 main b grayscale data registers (r81 to r84) the main b grayscale data registers specify the grayscale level of the b output in the main duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r81 0, 0 1 mbg4 mbg3 mbg2 mbg1 mbg0 r82 0, 1 1 mbg4 mbg3 mbg2 mbg1 mbg0 r83 1, 0 1 mbg4 mbg3 mbg2 mbg1 mbg0 r84 1, 1 1 mbg4 mbg3 mbg2 mbg1 mbg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 97 pd161401 6.48 sub r grayscale data registers (r85 to r92) the sub r grayscale data registers specify the grayscale level of the r output in the sub-duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r85 0, 0, 0 1 srg4 srg3 srg2 srg1 srg0 r86 0, 0, 1 1 srg4 srg3 srg2 srg1 srg0 r87 0, 1, 0 1 srg4 srg3 srg2 srg1 srg0 r88 0, 1, 1 1 srg4 srg3 srg2 srg1 srg0 r89 1, 0, 0 1 srg4 srg3 srg2 srg1 srg0 r90 1, 0, 1 1 srg4 srg3 srg2 srg1 srg0 r91 1, 1, 0 1 srg4 srg3 srg2 srg1 srg0 r92 1, 1, 1 1 srg4 srg3 srg2 srg1 srg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 98 pd161401 6.49 sub g grayscale data registers (r93 to r100) the sub g grayscale data registers specify the grayscale level of the g output in the sub-duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r93 0, 0, 0 1 sgg4 sgg3 sgg2 sgg1 sgg0 r94 0, 0, 1 1 sgg4 sgg3 sgg2 sgg1 sgg0 r95 0, 1, 0 1 sgg4 sgg3 sgg2 sgg1 sgg0 r96 0, 1, 1 1 sgg4 sgg3 sgg2 sgg1 sgg0 r97 1, 0, 0 1 sgg4 sgg3 sgg2 sgg1 sgg0 r98 1, 0, 1 1 sgg4 sgg3 sgg2 sgg1 sgg0 r99 1, 1, 0 1 sgg4 sgg3 sgg2 sgg1 sgg0 r100 1, 1, 1 1 sgg4 sgg3 sgg2 sgg1 sgg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 99 pd161401 6.50 sub b grayscale data registers (r101 to r104) the sub b grayscale data registers specify the grayscale level of the b output in the sub-duty display mode. by using these registers, grayscale display can be optimized. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r101 0, 0 1 sbg4 sbg3 sbg2 sbg1 sbg0 r102 0, 1 1 sbg4 sbg3 sbg2 sbg1 sbg0 r103 1, 0 1 sbg4 sbg3 sbg2 sbg1 sbg0 r104 1, 1 1 sbg4 sbg3 sbg2 sbg1 sbg0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 grayscale level 00000 level 0 00001 level 1 00010 level 2 00011 level 3 01111 level 15 10000 level 16 default value (default value of reset command, common to all grayscale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 note note note 00000 note 0 or 1
data sheet s15726ej2v0ds 100 pd161401 7. pd161401 register list (1/2) index register data bit cs rs 6543210 register name r/w 7 65432 1 0 1 0 0 ir index register w ir6 ir5 ir4 ir3 ir2 ir1 ir0 0 1 0 0 0 0 0 0 0 r0 control register 1 r/w tron was comf disp stby halt adc comr 0 1 0 0 0 0 0 0 1 r1 control register 2 r/w fdm bmod dty inc xdir ydir 0 1 0000010r2 0 1 0 0 0 0 0 1 1 r3 reset command w res 0 1 0 0 0 0 1 0 0 r4 x address register r/w xa6 xa5 xa4 xa3 xa2 xa1 xa0 0 1 0 0 0 0 1 0 1 r5 y address register r/w ya6 ya5 ya4 ya3 ya2 ya1 ya0 0 1 0000110r6 0 1 0000111r7 min. x address register r/w xmn6 xmn5 xmn4 xmn3 xmn2 xmn1 xmn0 0 1 0001000r8 max. x address register r/w xmx6 xmx5 xmx4 xmx3 xmx2 xmx1 xmx0 0 1 0001001r9 min. y address register r/w ymn6 ymn5 ymn4 ymn3 ymn2 ymn1 ymn0 0 1 0001010r10max. y address register r/w ymx6 ymx5 ymx4 ymx3 ymx2 ymx1 ymx0 0 1 0001011r11 0 1 0 0 0 1 1 0 0 r12 display memory access register d15 d14 d13 d15 d11 d10 d9 d8 w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0001101r13 0 1 0 0 0 1 1 1 0 r14 main duty setting register r/w mdt6 mdt5 mdt4 mdt3 mdt2 mdt1 mdt0 0 1 0 0 0 1 1 1 1 r15 main duty n-line inversion register r/w mid5 mid4 mid3 mid2 mid1 mid0 0 1 0 0 1 0 0 0 0 r16 main duty m-line shift register r/w msd5 msd4 msd3 msd2 msd1 msd0 0 1 0 0 1 0 0 0 1 r17 sub-duty setting register r/w sdt6 sdt5 sdt4 sdt3 sdt2 sdt1 sdt0 0 1 0 0 1 0 0 1 0 r18 sub-duty n-line inversion register r/w sid5 sid4 sid3 sid2 sid1 sid0 0 1 0 0 1 0 0 1 1 r19 sub-duty m-line shift register r/w ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 0 1 0010100r20 0 1 0 0 1 0 1 0 1 r21 com scanning address setting register r/w csa4 csa3 csa2 csa1 csa0 0 1 0 0 1 0 1 1 0 r22 sub-duty start address register r/w ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 0 1 0 0 1 0 1 1 1 r23 scroll fixed area position register r/w fixahl 0 1 0011000r24 0 1 0011001r25 0 1 0011010r26 0 1 0 0 1 1 0 1 1 r27 scroll fixed area width register r/w fixaw1 f ixaw0 0 1 0011100r28 0 1 0011101r29 0 1 0011110r30 0 1 0 0 1 1 1 1 1 r31 scroll step number register r/w mst6 mst5 mst4 mst3 mst2 mst1 mst0 0 1 0100000r32 0 1 0100001r33 0 1 0100010r34 0 1 0100011r35 0 1 0100100r36 0 1 0 1 0 0 1 0 1 r37 blink/reverse setting register r/w inv bld1 bld0 0 1 0 1 0 0 1 1 0 r38 complementary color blink x address register r/w cbx3 cbx2 cbx1 cbx0 0 1 0100111r39 complementary color blink start line address register r/w cbs6 cbs5 cbs4 cbs3 cbs2 cbs1 cbs0 0 1 0101000r40 complementary color blink end line address register r/w cbe6 cbe5 cbe4 cbe3 cbe2 cbe1 cbe0 0 1 0101001r41 complementary color blink data memory register w d7 d6d5d4d3d2 d1 d0 0 1 0 1 0 1 0 1 0 r42 specified color blinking x address register r/w sbx3 sbx2 sbx1 sbx0 0 1 0101011r43 specified color blink start line address register r/w sbs6 sbs5 sbs4 sbs3 sbs2 sbs1 sbs0 0 1 0101100r44 specified color blink end line address register r/w sbe6 sbe5 sbe4 sbe3 sbe2 sbe1 sbe0 0 1 0 1 0 1 1 0 1 r45 specified color blink data memory register w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 1 1 0 r46 specified color setting register r/w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 1 1 1 r47 reverse x address register r/w ivx3 ivx2 ivx1 ivx0 0 1 0 1 1 0 0 0 0 r48 reverse start line address register r/w ivs6 ivs5 ivs4 ivs3 ivs2 ivs1 ivs0 0 1 0 1 1 0 0 0 1 r49 reverse end line address register r/w ive6 ive5 ive4 ive3 ive2 ive1 ive0 0 1 0 1 1 0 0 1 0 r50 reverse data memory access register w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0110011r51 0 1 0 1 1 0 1 0 0 r52 power system control register 1 r/w tcs2 tcs1 tcs0 op3 op2 op1 op0 0 1 0 1 1 0 1 0 1 r53 power system control register 2 r/w vrr3 vrr2 vrr1 vrr0 svr3 svr2 svr1 svr0 0 1 0 1 1 0 1 1 0 r54 power system control register 3 r/w bis2 bis1 bis0 sbis2 sbis1 sbis0 0 1 0 1 1 0 1 1 1 r55 power system control register 4 r/w mbt2 mbt1 mbt0 sbt2 sbt1 sbt0 0 1 0 1 1 1 0 0 0 r56 power system control register 5 r/w lcs1 lcs0 lcc1 lcc0 hpm1 hpm0 psm1 psm0 0 1 0 1 1 1 0 0 1 r57 main electronic volume register r/w mev6 mev5 mev4 mev3 mev2 mev1 mev0 0 1 0 1 1 1 0 1 0 r58 sub-electronic volume register r/w sev6 sev5 sev4 sev3 sev2 sev1 sev0 0 1 0111011r59 0 1 0111100r60 0 1 0 1 1 1 1 0 1 r61 ram test mode setting register r/w rts2 rst1 rst0 0 1 0111110r62 0 1 0111111r63
data sheet s15726ej2v0ds 101 pd161401 (2/2) index register data bit cs rs 6543210 register name r/w 76543210 1 00 ir 0 1 1 0 0 0 0 0 0 r64 driving mode select register fxor 0 1 1 0 0 0 0 0 1 r65 main r grayscale data register 1 (0, 0, 0) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 0 1 0 r66 main r grayscale data register 2 (0, 0, 1) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 0 1 1 r67 main r grayscale data register 3 (0, 1, 0) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 1 0 0 r68 main r grayscale data register 4 (0, 1, 1) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 1 0 1 r69 main r grayscale data register 5 (1, 0, 0) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 1 1 0 r70 main r grayscale data register 6 (1, 0, 1) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 0 1 1 1 r71 main r grayscale data register 7 (1, 1, 0) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 1 0 0 0 r72 main r grayscale data register 8 (1, 1, 1) mrg4 mrg3 mrg2 mrg1 mrg0 0 1 1 0 0 1 0 0 1 r73 main g grayscale data register 1 (0 ,0, 0) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 0 1 0 r74 main g grayscale data register 2 (0, 0, 1) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 0 1 1 r75 main g grayscale data register 3 (0, 1, 0) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 1 0 0 r76 main g grayscale data register 4 (0, 1, 1) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 1 0 1 r77 main g grayscale data register 5 (1, 0, 0) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 1 1 0 r78 main g grayscale data register 6 (1, 0, 1) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 0 1 1 1 1 r79 main g grayscale data register 7 (1, 1, 0) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 1 0 0 0 0 r80 main g grayscale data register 8 (1, 1, 1) mgg4 mgg3 mgg2 mgg1 mgg0 0 1 1 0 1 0 0 0 1 r81 main b grayscale data register 1 (0, 0) mbg4 mbg3 mbg2 mbg1 mbg0 0 1 1 0 1 0 0 1 0 r82 main b grayscale data register 2 (0, 1) mbg4 mbg3 mbg2 mbg1 mbg0 0 1 1 0 1 0 0 1 1 r83 main b grayscale data register 3 (1, 0) mbg4 mbg3 mbg2 mbg1 mbg0 0 1 1 0 1 0 1 0 0 r84 main b grayscale data register 4 (1, 1) mbg4 mbg3 mbg2 mbg1 mbg0 0 1 1 0 1 0 1 0 1 r85 sub r grayscale data register 1 (0, 0, 0) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 0 1 1 0 r86 sub r grayscale data register 2 (0, 0, 1) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 0 1 1 1 r87 sub r grayscale data register 3 (0, 1, 0) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 0 0 0 r88 sub r grayscale data register 4 (0, 1, 1) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 0 0 1 r89 sub r grayscale data register 5 (1, 0, 0) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 0 1 0 r90 sub r grayscale data register 6 (1, 0, 1) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 0 1 1 r91 sub r grayscale data register 7 (1, 1, 0) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 1 0 0 r92 sub r grayscale data register 8 (1, 1, 1) srg4 srg3 srg2 srg1 srg0 0 1 1 0 1 1 1 0 1 r93 sub g grayscale data register 1 (0, 0, 0) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 0 1 1 1 1 0 r94 sub g grayscale data register 2 (0, 0, 1) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 0 1 1 1 1 1 r95 sub g grayscale data register 3 (0, 1, 0) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 0 0 0 r96 sub g grayscale data register 4 (0, 1, 1) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 0 0 1 r97 sub g grayscale data register 5 (1, 0, 0) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 0 1 0 r98 sub g grayscale data register 6 (1, 0, 1) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 0 1 1 r99 sub g grayscale data register 7 (1, 1, 0) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 1 0 0 r100 sub g grayscale data register 8 (1, 1, 1) sgg4 sgg3 sgg2 sgg1 sgg0 0 1 1 1 0 0 1 0 1 r101 sub b grayscale data register 1 (0, 0) sbg4 sbg3 sbg2 sbg1 sbg0 0 1 1 1 0 0 1 1 0 r102 sub b grayscale data register 2 (0, 1) sbg4 sbg3 sbg2 sbg1 sbg0 0 1 1 1 0 0 1 1 1 r103 sub b grayscale data register 3 (1, 0) sbg4 sbg3 sbg2 sbg1 sbg0 0 1 1 1 0 1 0 0 0 r104 sub b grayscale data register 4 (1, 1) sbg4 sbg3 sbg2 sbg1 sbg0 0 1 1101001r105 0 1 1101010r106 0 1 1101011r107 0 1 1101100r108 0 1 1101101r109 0 1 1101110r110 0 1 1101111r111 0 1 1110000r112 0 1 1110001r113 0 1 1110010r114 0 1 1110011r115 0 1 1110100r116 0 1 1110101r117 0 1 1110110r118 0 1 1110111r119 0 1 1111000r120 0 1 1111001r121 0 1 1111010r122 0 1 1111011r123 0 1 1111100r124 0 1 1111101r125 0 1 1111110r126 0 1 1111111r127
data sheet s15726ej2v0ds 102 pd161401 8. power sequence the pd161401 has on-chip power circuits such as a booster circuit and a voltage follower circuit. resetting by the /disp pin should only be used to prevent malfunctioning due to noise. if charge remains in the smoothing capacitor connected between the lcd drive pins (v lcd , v lc1 to v lc4 ) and v ss , the display screen may momentarily blackout when power is turned on or off. it is therefore recommended to turn on/off power in the following sequence to avoid any trouble.
data sheet s15726ej2v0ds 103 pd161401 8.1 power on sequence (with internal power supply, power on display on) power on when /disp pin = l power supply is stabilized. /disp pin = h wait for 50 s or more. reset command r3 initialization of registers control register 1 disp = 0, halt = 1 r0 display off. internal operation stops. ic function setting by command input 1 control register 1 (disp = 0, halt = 1) control register 2 ic function setting by command input 2 power system control register 1 (op3, op2, op1, op0 = 1, 1, 1, 1) power system control registers 2, 3, and 4 power system control register 5 (hpm1, hpm0 = 0, 1) main electronic volume register sub-electronic volume register specify power on mode 1 (master ic only). user setting by command input setting of functions such as grayscale data initialization complete control register 1 (dips = 0, halt = 0 ) r0 display off. internal operation starts. lcd display screen setting display start line set writing of screen data + wait time wait time 1 wait for 120 to 150 ms or more from when the internal operation starts until the lcd turns on note . power system control register 5 (hpm1, hpm0 = 0, 0) (lcs1, lcs0 = 1,1) (lcc1, lcc0 = 1,1) (psm = 1) change the operation mode of the operation amplifier to ?normal mode? (master ic only). segment output driving capability setting: x8 common output driving capability setting: x16 voltage follower bias current: x2 in the next page note the wait times1, 2 vary depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system (refer to 8.5 flow of v out and v lcd voltages from power on to power off ).
data sheet s15726ej2v0ds 104 pd161401 wait time 2 wait for at least 250 ms from when the output mode of the operation amplifier is changed until the lcd turns on note . power system control register 5 (hpm1, hpm0 = 0, 0) (lcs1, lcs0 = x,x) (lcc1, lcc0 = x,x) (psm = x) r0 the operation mode of the operation amplifier: normal mode change the setting of the segment output driving capability, common output driving capability, and voltage follower bias current to the normal state. control register 1 (dips = 1, halt = 0 ) r0 display on. internal operation starts. x: 0 or 1 note the wait times1, 2 vary depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system (refer to 8.5 flow of v out and v lcd voltages from power on to power off ).
data sheet s15726ej2v0ds 105 pd161401 8.2 power off sequence (with internal power supply) operation status control register 1 disp = 0, halt = 0 r0 display off . internal operation starts. power system control register 5 (hpm1, hpm0 = 1, 0) r56 change the operation mode of the operational amplifier to ?power off mode?. main electronic volume register setting r57 [mev6, mev5, mev4, mev3, mev2, mev1, mev0] = [0, 0, 0, 0, 0, 0, 0] sub-electronic volume register setting r58 [sev6, sev5, sev4, sev3, sev2, sev1, sev0] = [0, 0, 0, 0, 0, 0, 0] wait time 1 wait for at least 120 ms note . control register 1 (disp = 0, halt = 1) r0 display off. internal operation stops. wait time 2 wait for at least 380 ms before turning power off note . power off note the wait times 1, 2 vary depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system (refer to 8.5 flow of v out and v lcd voltages from power on to power off ).
data sheet s15726ej2v0ds 106 pd161401 8.3 power on sequence (with external driving power supply, power on display on) this is an example of inputting a reference voltage to the v rs pin and a driving voltage to the v out pin from an external power supply. logic power supply on with /disp pin = l v dd1 and v dd2 on, v out = hi-z power supply stabilized. /disp pin = h wait for 50 s or more. reset command r3 initialization of registers control register 1 disp = 0, halt = 1 r0 display off. internal operation stops. ic function setting by command input 1 control register 1 (disp = 0, halt = 1) control register 2 ic function setting by command input 2 power system control register 1 (op3, op2, op1, op0 = 1, 1, 1, 1) power system control registers 2, 3, and 4 power system control register 5 (hpm1, hpm0 = 0, 1) main electronic volume register sub-electronic volume register specify power on mode1 (master ic only). user setting by command input setting of functions such as grayscale data initialization complete control register 1 (disp = 0, halt = 0 ) r0 display off. internal operation starts. turn on external driving power supply supply voltage to v out pin. lcd screen setting display start line setting writing of screen data + wait time wait for at least 300 ms from when the internal operation starts until the lcd turns on note . power system control register 5 (hpm1, hpm0 = 0, 0) change the operation mode of the operation amplifier to ?normal mode? (master ic only). control register 1 (dips = 1 , halt = 0) r0 display on. internal operation starts. note the time of 300 ms varies depending on the characteristics of the lcd panel and the capacitance of the smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system (refer to 8.5 flow of v out and v lcd voltages from power on to power off ).
data sheet s15726ej2v0ds 107 pd161401 8.4 power off sequence (with external driving power supply) this is an example of inputting a reference voltage to the v rs pin and a driving voltage to the v out pin from an external power supply. operation status control register 1 disp = 0, halt = 0 r0 display off. internal operation starts. power system control register 5 (hpm1, hpm0 = 1, 0) r56 change the operation mode of the operational amplifier to ?power off mode?. wait for at least 300 ms until power is off note . driving power supply off turn off driving voltage v out after the levels of v lcd and v lc1 to v lc4 have completely dropped. power off power to v dd1 and v dd2 off note the time of 300 ms varies depending on the characteristics of the lcd panel and the capacitance of the smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system (refer to 8.5 flow of v out and v lcd voltages from power on to power off ).
data sheet s15726ej2v0ds 108 pd161401 8.5 flow of v out and v lcd voltages from power on to power off v out v dd 0 hpm = 0,0(m) sub duty display main duty display normal duty display halt = 0 v dd on tcs = 0,1,1(m) op = 1,1,1,1 (m) /disp pin = l res = 1 120 to 150 ms disp = 0, halt = 1 disp = 1 disp = 1 disp = 1 disp = 0 hpm = 1,0(m) dty = 1 disp = 0 hpm = 0,1(m) dty = 0 disp = 0 ev = 0 pev = 0(m) v dd off dotted line: v out solid line: v lcd 120 ms 160 ms 50 ms /disp pin = h hpm = 0,0(m) hpm = 1,0(m) halt = 1 lcs = 1,1 lcc = 1,1 hpm = 0,1 (m) lcs = 1,1 lcc = 1,1 hpm = 0,0 (m) 250 ms 150 ms hpm = 0,1(m) 380 ms lcs = x,x lcc = x,x hpm = 0,0 (m) x: 1 or 0 test conditions: supply voltage: v dd1 = v dd2 = 3.0 v number of boosting stages: x5 (in normal display mode), x3 (in partial display mode) capacitance: between v lcn pin and c n +/- pins = 1.0 f caution connect a capacitor of 0.1 f or less to the amp outm and amp outs pins.
data sheet s15726ej2v0ds 109 pd161401 8.6 flow of v out and v lcd voltages in display output and halt/standby modes v out v dd 0 main duty display disp = 0 ev = 0 dotted line: v out solid line: v lcd 160 ms halt(stby) hpm = 1,0(m) halt = 0(stby = 0) disp = 1 hpm = 0,0(m) halt = 1(stby = 1) ev = x,x(m) hpm = 0,1(m) 300 ms x: 1 or 0 test conditions: supply voltage: v dd1 = v dd2 = 3.0 v. number of boosting stages: x5 (in normal display mode), x3 (in partial display mode) capacitance: between v lcn pin and c n +/- pins = 1.0 f caution connect a capacitor of 0.1 f or less to the amp outm and amp outs pins.
data sheet s15726ej2v0ds 110 pd161401 9. using ram test mode the pd161401 has a test mode in which seven types of screen data are written to the display ram. when using this test mode, be sure to execute the following sequence. if the ram test mode is executed in any other sequence, erroneous data may be displayed. operating status control register 1 disp = 0, stby = 1 r0 display off. standby setting ram test mode setting r61 select data to be written to ram. control register 1 disp = 0, stby = 0 r0 display off. standby cleared wait time wait for 200 ms or more from when the internal operation starts until the lcd turns off note . control register 1 disp = 1 r0 display on. setting complete note the time of 200 ms varies depending on the characteristics of the lcd panel and the capacitance of the boosting or smoothing capacitor. it is recommended to determine this value after thorough evaluation with the actual system. remark the set display data is always written to the display ram in the ram test mode.
data sheet s15726ej2v0ds 111 pd161401 10. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol ratings unit logic supply voltage v dd1 ? 0.3 to +4.0 v booster circuit supply voltage v dd2 ? 0.3 to +4.0 v driver supply voltage v out ? 0.3 to +20.0 v driver reference power input voltage v lcd ,v lc1 to v lc4 ? 0.3 to v out + 0.3 v logic input voltage v in1 ? 0.3 to v dd1 + 0.3 v logic output voltage v o1 ? 0.3 to v dd1 + 0.3 v logic i/o voltage v i/o1 ? 0.3 to v dd1 + 0.3 v driver input voltage v in2 ? 0.3 to v out + 0.3 v driver output voltage v o2 ? 0.3 to v out + 0.3 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range parameter symbol min. typ. max. unit logic supply voltage v dd1 1.8 3.6 v booster circuit supply voltage v dd2 note1 2.4 3.6 v driver supply voltage v out note2 5.5 18.0 v logic supply voltage v in 0v dd1 v driver supply voltage v lcd , v lc1 to v lc4 note2 0v out v maximum lcd voltage setting range v lcd note3 v out ? 0.5 v notes 1. it is essential that v dd1 v dd2 . 2. these conditions are recommended when the lcd is driven by an external power supply. 3. this condition is recommended when the lcd is driven by the internal power supply circuit. cautions 1. make sure that the relationship of v ss < v lc4 < v lc3 < v lc2 data sheet s15726ej2v0ds 112 pd161401 electrical specifications (unless otherwise specified, t a = ? ? ? ? 40 to +85 c, v dd1 = 1.8 to 3.6 v, v dd2 = 2.4 to 3.6 v.) parameter symbol conditions min. typ. notes1 max. unit input voltage, high v ih 0.8 v dd1 v input voltage, low v il 0.2 v dd1 v input current, high i ih1 other than d 15 to d 0 1 a input current, low i il1 other than d 15 to d 0 ? 1 a output voltage, high v oh i out = ? 1 ma. other than ocs out v dd1 ? 0.5 v output voltage, low v ol i out = 1 ma. other than ocs out 0.5 v leakage current, high i loh d 15 to d 8 , d 7 (si), d 6 (scl), d 5 to d 0 , v in/out = v dd1 10 a leakage current, low i lol d 15 to d 8 , d 7 (si), d 6 (scl), d 5 to d 0 , v in/out = v ss ? 10 a common output on resistance r com v lcn com n , v out = 15 v, v lcd = 13 v, 1/9 bias, |i o | = 50 a 4k ? segment output on resistance r seg v lcn seg n , v out = 15 v, v lcd = 13 v, 1/9 bias, |i o | = 50 a 4k ? driver voltage (booster voltage) v out in 5-fold mode, v dd2 = 3.0 v, diced display 13.8 v in 6-fold mode, v dd2 = 3.0 v, diced display 16.6 v regulated voltage notes2 v reg t a = 85 c. (tcs2, tcs1, tcs0) = (0,1,0) temperature curve ?0.15 %/ c 1.430 1.485 1.540 v ? v lcn v lcn : v lcd , v lc1 to v lc4 , (op3, op2, op1, op0) = (0, 0, 0, 1) v dd1 = 2.5 v, v out = 15 v, amp outm = 14 v, bias = 1/5 to 1/9, irs pin = l, display off, no load ? 50 50 mv output voltage deflection ? amp out irs pin = h, 1+rb/ra = 10-fold ? 100 100 mv oscillation frequency notes3 v dd1 = 3.0 v, t a = 25 c, 1/80 duty, r = 360 k ? (osc in1 -osc out ) 72 85 97 khz f osc v dd1 = 3.0 v, t a = 25 c, 1/38 duty, r = 770 k ? (osc in2 -osc out ) 33 40 46 khz current consumption i dd11 frame frequency = 70 hz, all pwm display output, 1/80 duty, v dd1 = v dd2 = 3.0 v, v lcd = 13 v, in 5-fold mode, driving mode (segment x 1, common x 4) 175 280 a frame frequency = 70 hz, all pwm display output, 1/32 duty, v dd1 = v dd2 = 3.0 v, v lcd = 7.0 v, in 3-fold mode, driving mode (segment x 1, common x 4) 72 120 a current consumption (standby mode) i dd22 v dd1 = v dd2 = 3.0 v 10 a notes1 the typ. values are reference values at t a = 25 c (except for regulated voltage (v reg )). 2 the typ. values of regulated voltage (v reg ) at t a = 25 c are min. 1.580 v, typ. 1.635 v, max. 1.690 v 3 oscillation frequency is changed under the influence of the wiring capacity to the external resistor for oscillation.
data sheet s15726ej2v0ds 113 pd161401 timing requirements (unless otherwise specified, t a = ? ? ? ? 30 to +85 c.) (1) i80 cpu interface t as8 t ah8 t cclr , t cclw t cyc8 t cchr , t cchw t dh8 t ds8 t acc8 t oh8 rs /cs1 (cs2 = h) /wr, /rd d 0 to d 15 (d 7 ) (write) (read) t f t r d 0 to d 7 (v dd1 = 1.8 to 2.0 v) parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 1000 ns control l pulse width (/wr) t cclw /wr 160 ns control l pulse width (/rd) t cclr /rd 430 ns control h pulse width (/wr) t cchw /wr 160 ns control h pulse width (/rd) t cchr /rd 160 ns data setup time t ds8 d 0 to d 15 (d 7 ) 160 ns data hold time t dh8 d 0 to d 15 (d 7 )0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 470 ns output disable time t oh8 d 0 to d 7 , c l = 5 pf, r l = 3 k ? 0 170 ns note the typ. values are reference values at t a = 25 c. (v dd1 = 2.0 to 2.5 v) parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 600 ns control l pulse width (/wr) t cclw /wr 120 ns control l pulse width (/rd) t cclr /rd 240 ns control h pulse width (/wr) t cchw /wr 120 ns control h pulse width (/rd) t cchr /rd 120 ns data setup time t ds8 d 0 to d 15 (d 7 ) 120 ns data hold time t dh8 d 0 to d 15 (d 7 )0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 280 ns output disable time t oh8 d 0 to d 7 , c l = 5 pf, r l = 3 k ? 0 170 ns note the typ. values are reference values at t a = 25 c.
data sheet s15726ej2v0ds 114 pd161401 (v dd1 = 2.5 to 3.6 v) parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 100 ns control l pulse width (/wr) t cclw /wr 40 ns control l pulse width (/rd) t cclr /rd 40 ns control h pulse width (/wr) t cchw /wr 40 ns control h pulse width (/rd) t cchr /rd 40 ns data setup time t ds8 d 0 to d 15 (d 7 )40ns data hold time t dh8 d 0 to d 15 (d 7 )0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 50 ns output disable time t oh8 d 0 to d 7 , c l = 5 pf, r l = 3 k ? 050ns note the typ. values are reference values at t a = 25 c. cautions 1. the rise and fall times (t r and t f ) of an input signal are 10 ns or less. 2. all timing data is specified at 20% and 80% of v dd1 .
data sheet s15726ej2v0ds 115 pd161401 (2) m68 cpu interface t as6 t ah6 t ewhr , t ewhw t cyc6 t ewlr , t ewlw t dh6 t ds6 t acc6 t oh6 rs r,/w /cs1 (cs2 = h) e d 0 to d 15 (d 7 ) (write) d 0 to d 7 (read) t f t r (v dd1 = 1.8 to 2.0 v) parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 1000 ns data setup time t ds6 d 0 to d 15 (d 7 ) 160 ns data hold time t dh6 d 0 to d 15 (d 7 )0 ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 470 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns enable h pulse width read t ewhr e 430 ns write t ewhw e 160 ns enable l pulse width read t ewlr e 160 ns write t ewlw e 160 ns note the typ. values are reference values at t a = 25 c. (v dd1 = 2.0 to 2.5 v) parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 600 ns data setup time t ds6 d 0 to d 15 (d 7 ) 120 ns data hold time t dh6 d 0 to d 15 (d 7 )0 ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 280 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns enable h pulse width read t ewhr e 240 ns write t ewhw e 120 ns enable l pulse width read t ewlr e 120 ns write t ewlw e 120 ns note the typ. values are reference values at t a = 25 c.
data sheet s15726ej2v0ds 116 pd161401 (v dd1 = 2.5 to 3.6 v) parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 100 ns data setup time t ds6 d 0 to d 15 (d 7 )50 ns data hold time t dh6 d 0 to d 15 (d 7 )0 ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 50 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 050ns enable h pulse width read t ewhr e40ns write t ewhw e40ns enable l pulse width read t ewlr e40ns write t ewlw e40ns note the typ. values are reference values at t a = 25 c. cautions 1. the rise and fall times (t r and t f ) of an input signal are 10 ns or less. if the system cycle time is short, (t r + t f ) (t cyc6 ? t ewlw ? t ewhw ) or (t r + t f ) (t cyc6 ? t ewlr ? t ewhr ). 2. all timing data is specified at 20% and 80% of v dd1 .
data sheet s15726ej2v0ds 117 pd161401 (3) serial interface t css t f t r t csh t sas t sah t slw t shw t scyc t sds t sdh /cs1 (cs2 = h) rs scl si (v dd1 = 1.8 to 2.5 v) parameter symbol condition min. typ. note max. unit serial clock cycle t scyc scl 250 ns scl high-level pulse width t shw scl 100 ns scl low-level pulse width t slw scl 100 ns address hold time t sah rs 150 ns address setup time t sas rs 150 ns data setup time t sds si 100 ns data hold time t sdh si 100 ns cs - scl time t css /cs1 (cs2 = h) 150 ns t csh /cs1 (cs2 = h) 150 ns note typ. values are reference values when t a = 25 c. (v dd1 = 2.5 to 3.6 v) parameter symbol condition min. typ. note max. unit serial clock cycle t scyc scl 150 ns scl high-level pulse width t shw scl 60 ns scl low-level pulse width t slw scl 60 ns address hold time t sah rs 90 ns address setup time t sas rs 90 ns data setup time t sds si 60 ns data hold time t sdh si 60 ns cs - scl time t css /cs1 (cs2 = h) 90 ns t csh /cs1 (cs2 = h) 90 ns note typ. values are reference values when t a = 25 c. cautions 1 . the rise and fall times of input signal (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20% and 80% of v dd1 .
data sheet s15726ej2v0ds 118 pd161401 (4) common parameter symbol conditions min. typ. note max. unit clock input 1 f m osc in1 . external clock is used in main duty display mode,1/80 duty 85 khz clock input 2 f s osc in2 . external clock is used in sub-duty display mode, 1/40 duty 40 khz note the typ. values are reference value at a frame frequency = 70 hz. cautions 1. the rise time and fall time (t r and t f ) of an input signal is 15 ns or less. 2. all timing data is specified at 20% and 80% of v dd1 . (a) timing of display control output t dfr osc sync (out) fr (v dd1 = 1.8 to 2.5 v) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 50 200 ns note the typ. values are reference values at t a = 25 c. (v dd1 = 2.5 to 3.6 v) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 20 80 ns note the typ. values are reference values at t a = 25 c. caution all timing data is specified at 20% and 80% of v dd1 .
data sheet s15726ej2v0ds 119 pd161401 (b) reset timing t rw t r reset end of reset /disp internal status (v dd1 = 1.8 to 2.5 v) parameter symbol conditions min. typ. note max. unit reset time t r 50 s reset l pulse width t rw /disp 50 s note the typ. values are reference values at t a = 25 c. (v dd1 = 2.5 to 3.6 v) parameter symbol conditions min. typ. note max. unit reset time t r 50 s reset l pulse width t rw /disp 50 s note the typ. values are reference values at t a = 25 c. caution all timing data is specified at 20% and 80% of v dd1 .
data sheet s15726ej2v0ds 120 pd161401 11. cpu interface (reference example) the pd161401 can be connected to both an i80 system cpu and a m68 system cpu. in addition, the number of signal lines can be reduced by using the serial interface. the display area can be expanded by using two or more pd161401 chips. in this case, each ic is selected and accessed by a chip select signal. decoder rs d 0 to d 15 e /disp a 0 e r,/w /res vima a 1 to a 15 /cs1 v dd1 v cc gnd v ss /res cpu r,/w ifm0 ifm1 decoder rs d 0 to d 15 /rd /wr /disp a 0 /rd /wr /res /iorq a 1 to a 7 /cs1 v dd1 v cc gnd v ss /res cpu ifm0 ifm1 (1) m68 series cpu (2) i80 series cpu
data sheet s15726ej2v0ds 121 pd161401 [memo]
data sheet s15726ej2v0ds 122 pd161401 [memo]
data sheet s15726ej2v0ds 123 pd161401 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161401 m8e 00. 4 the information in this document is current as of june, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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